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ASIC interview question topics, organized for focused practice

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Reusable verification architecture

UVM Interview Questions

Practice UVM interview questions on phases, factory overrides, config_db, sequences, drivers, monitors, scoreboards, TLM, and reusable verification IP.

  • Phases
  • Objections
  • config_db
Open topic
Verification intent to closure evidence

Coverage Interview Questions

Practice coverage interview questions on code coverage, functional coverage, covergroups, bins, crosses, sampling, UVM ownership, regression merging, and closure.

  • Coverage plan
  • Code coverage
  • Traceability
Open topic
Behavior to synthesizable hardware

RTL Design Interview Questions

Practice RTL design interview questions on combinational and sequential logic, FIFOs, FSMs, ready-valid flow control, arithmetic, and synthesis intent.

  • Muxes
  • Arithmetic
  • Latch avoidance
Open topic
Netlist to testable, signoff-ready silicon

DFT, Physical Design, and Signoff Interview Questions

Practice DFT, physical design, and signoff interview questions on scan, ATPG, MBIST, floorplanning, clock trees, routing, STA, power integrity, and closure.

  • RTL-to-GDS
  • Handoffs
  • Extraction
Open topic
Safe boundaries between clock domains

CDC and Reset Interview Questions

Practice CDC and reset interview questions on metastability, synchronizers, handshakes, asynchronous FIFOs, Gray pointers, reset release, and timing constraints.

  • Metastability
  • Two-flop synchronizers
  • Pulses
Open topic
Turn temporal intent into executable checks

SystemVerilog Assertions Interview Questions

Practice SystemVerilog Assertions interview questions on implication, repetition, sampling, disable iff, vacuity, protocol properties, and formal verification.

  • Implication
  • Repetition
  • $past
Open topic
Generate legal, useful stimulus

SystemVerilog Constraints Interview Questions

Practice SystemVerilog constraint interview questions on inside, dist, solve before, unique values, arrays, alignment, stateful randomization, and solver behavior.

  • inside
  • dist
  • Alignment
Open topic
Classes, identity, and reusable verification code

SystemVerilog OOP Interview Questions

Review classes, handles, constructors, inheritance, polymorphism, virtual methods, casting, copying, and verification-oriented design patterns.

  • Classes and handles
  • Virtual dispatch
  • Copying and patterns
Open topic
Software at the hardware boundary

Firmware Interview Questions for ASIC Engineers

Practice firmware interview questions on interrupts, DMA, MMIO, drivers, fixed-memory algorithms, protocol timing, bring-up, and hardware-software debugging.

  • MMIO
  • Interrupts
  • DMA
Open topic