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ASIC interview question topics, organized for focused practice
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Reusable verification architecture
UVM Interview Questions
Practice UVM interview questions on phases, factory overrides, config_db, sequences, drivers, monitors, scoreboards, TLM, and reusable verification IP.
- Phases
- Objections
- config_db
Verification intent to closure evidence
Coverage Interview Questions
Practice coverage interview questions on code coverage, functional coverage, covergroups, bins, crosses, sampling, UVM ownership, regression merging, and closure.
- Coverage plan
- Code coverage
- Traceability
Behavior to synthesizable hardware
RTL Design Interview Questions
Practice RTL design interview questions on combinational and sequential logic, FIFOs, FSMs, ready-valid flow control, arithmetic, and synthesis intent.
- Muxes
- Arithmetic
- Latch avoidance
Netlist to testable, signoff-ready silicon
DFT, Physical Design, and Signoff Interview Questions
Practice DFT, physical design, and signoff interview questions on scan, ATPG, MBIST, floorplanning, clock trees, routing, STA, power integrity, and closure.
- RTL-to-GDS
- Handoffs
- Extraction
Safe boundaries between clock domains
CDC and Reset Interview Questions
Practice CDC and reset interview questions on metastability, synchronizers, handshakes, asynchronous FIFOs, Gray pointers, reset release, and timing constraints.
- Metastability
- Two-flop synchronizers
- Pulses
Turn temporal intent into executable checks
SystemVerilog Assertions Interview Questions
Practice SystemVerilog Assertions interview questions on implication, repetition, sampling, disable iff, vacuity, protocol properties, and formal verification.
- Implication
- Repetition
- $past
Generate legal, useful stimulus
SystemVerilog Constraints Interview Questions
Practice SystemVerilog constraint interview questions on inside, dist, solve before, unique values, arrays, alignment, stateful randomization, and solver behavior.
- inside
- dist
- Alignment
Handshake rules to end-to-end evidence
AXI, APB, AHB, and Ready/Valid Verification Interview Questions
Practice protocol-verification interview questions on ready/valid flow control, APB setup and access phases, AHB pipelining, AXI channel independence, bursts, IDs, ordering, scoreboards, assertions, coverage, and negative testing.
- Ready/valid
- APB phases
- AHB pipeline
Bits, collections, identity, and representation
SystemVerilog Data Types Interview Questions
Practice SystemVerilog data type interview questions on 2-state and 4-state values, packed and unpacked arrays, queues, dynamic and associative arrays, structs, unions, enums, strings, casts, and DPI boundaries.
- 2-state vs 4-state
- Sizing and casts
- Equality
Processes, subroutines, assignment, and scheduling intent
SystemVerilog Procedural Blocks Interview Questions
Practice SystemVerilog procedural-block interview questions on initial and always processes, always_comb, always_ff, tasks, functions, automatic lifetime, program and clocking blocks, DPI, blocking and nonblocking assignment, case semantics, and inferred hardware.
- initial and always
- Tasks
- Functions
Parallel processes, synchronization, and safe shutdown
SystemVerilog Concurrency Interview Questions
Practice SystemVerilog concurrency interview questions on fork-join variants, process handles, events, semaphores, mailboxes, wait fork, disable fork, timeouts, deadlock, races, and deterministic parallel testbench control.
- fork...join
- join_any
- join_none
Classes, identity, and reusable verification code
SystemVerilog OOP Interview Questions
Review classes, handles, constructors, inheritance, polymorphism, virtual methods, casting, copying, and verification-oriented design patterns.
- Classes and handles
- Virtual dispatch
- Copying and patterns
Software at the hardware boundary
Firmware Interview Questions for ASIC Engineers
Practice firmware interview questions on interrupts, DMA, MMIO, drivers, fixed-memory algorithms, protocol timing, bring-up, and hardware-software debugging.
- MMIO
- Interrupts
- DMA
Canonical question directory
Every public question, one stable link.
Browse the first 200 questions and selected Free previews by topic. Each title opens its crawlable question page with the full prompt and available public teaching support.
Browse all 201 public questions46 technical categories · full question-title links+
Arbiters1
Arrays3
Bit Manipulation2
CDC & RDC3
CDC and Reset2
CDC Verification1
Clock and Reset2
Clock and Reset Domains1
Clock Domain Crossing4
Coherence1
Computer Architecture2
Constraints2
Data Structures17
- Q012Implement and verify a bounded queue
- Q016Packed and unpacked arrays
- Q042Return the first unique value in a stream
- Q049Dynamic-array resizing
- Q071Dynamic arrays and queues
- Q094Implement a simple least-recently-used cache
- Q095Build an interrupt-safe sliding-maximum telemetry filter
- Q104Merge frozen per-core crash logs without allocation
- Q132Replace top-K sorting with frequency buckets
- Q139Make the least-recently-used cache O(1)
- Q145Track top-K frequencies in a sliding window
- Q150Estimate stream frequencies with a Count-Min Sketch
- Q154Expiring Key-Value Store
- Q169Insert, remove, and sample in average O(1)
- Q176Maintain the K largest stream values
- Q182Use lower-bound insertion for top-K largest
- Q195Associative-array traversal
DFT1
DFT & Physical Design1
Firmware Algorithms7
Formal Verification1
FSMs1
Functional Coverage2
Hardware Algorithms4
Hardware-Software Integration4
Low Power1
Matrices1
Memory Systems9
- Q013Find the densest 4 KiB page
- Q021Look up time-indexed register history
- Q028Verify a RAM-based duplicate-ID detector
- Q034Measure external fragmentation
- Q113Verify a channel-capacity optimizer
- Q128Build a first-fit range allocator
- Q138Rotate a tile in place with one memory port
- Q157Return every page at the kth density rank
- Q194Allocate on a power-of-two boundary
Performance Analysis1
Physical Design2
Protocol Checking2
Reference Models19
- Q026Retire out-of-order completions in order
- Q033Match out-of-order packets by ID
- Q038Verify a mirrored topology checker
- Q048Verify matrix zero propagation
- Q053Out-of-order scoreboard matching
- Q061Check delayed and reordered memory writes
- Q067Check a per-ID latency window
- Q072Verify signed maximum-product ranges
- Q084Priority Interrupt Controller Reference Model
- Q092Verify a minimum energy-window engine
- Q098Verify a bounded step-sequence counter
- Q103Verify unique zero-sum triplets
- Q117Model sparse banked memory with packed keys
- Q130Verify a shared-memory spiral readout
- Q135Verify duplicate token supply
- Q147Scoreboard a maximum-interval accelerator
- Q160Verify a retained-memory water accelerator
- Q179Expire memory expectations without full scans
- Q197Monitor an independently stalled binary adder
Reliable RTL2
Reset Design1
RTL Arithmetic1
RTL Datapaths5
RTL Design28
- Q006Vote across redundant state monitors
- Q007Build a synchronous FIFO and race-free BFM
- Q014Register a glitch-free decoded enable
- Q020Absorb ready/valid backpressure with a skid buffer
- Q025Stably sort records in a local cache-line buffer
- Q031Coalesce a frame of DMA ranges
- Q041Control a tiny exact-LRU associative cache
- Q063Predict Priority from If and Case Statements
- Q069Find the lowest set lane
- Q074Overlapping 101 sequence detector
- Q079Build a reloadable countdown timer
- Q085Schedule bank commands with accepted-slot cooldown
- Q090Increment a four-digit BCD counter
- Q096Count connected fault regions in a tile map
- Q102Code an asynchronously reset register with enable
- Q109Enforce simplified per-bank command timing
- Q129Average four accepted samples
- Q134Route a shared read bus without internal tri-states
- Q141Decode Z wildcards without hiding X
- Q146Choose Mealy timing for an immediate match
- Q149Diagnose storage from an incomplete always_comb block
- Q156Build one-write/two-read memory from BRAM
- Q162Reverse a physical bus at the lane boundary
- Q168Count active lanes in a predicate mask
- Q174Order the major digital ASIC development stages
- Q177Implement a parameterized binary-to-Gray converter
- Q191Pipeline a parameterized barrel rotator
- Q193Implement a divide-by-four clock model
Sequential RTL1
Streaming Algorithms4
Streaming RTL5
Strings2
SystemVerilog2
Temporal Checks6
Testbench Concurrency1
Timing4
Timing & STA2
Timing Models1
UVM Components13
- Q008uvm_object versus uvm_component
- Q044Config_db virtual interface distribution
- Q062Verify a cascading flit-collision resolver
- Q077Get_next_item and item_done
- Q087Verify a return-stack trace validator
- Q106Verify a framed cache-line rotator
- Q119Verify a RAL-programmed grid checker
- Q155Sequence response queue depth
- Q165End run phase with a forever monitor
- Q170Analysis port semantics
- Q175Multi-sequence response routing
- Q183Check_phase and final checking
- Q192Sequencer locks and grabs
Verification Utilities3
Waveform Debugging23
- Q002Valid Drops During a Stall
- Q019Pipeline Returns the Wrong Tag
- Q024FIFO Returns the Wrong Head Entry
- Q029Unknown Output After Reset
- Q035AXI Write Address Changes While Stalled
- Q040Second Synchronizer Stage Changes Too Soon
- Q060Sticky Interrupt Does Not Clear
- Q070AXI Write Response Is Issued Too Early
- Q075Short CDC Pulse Is Not Seen in the Destination
- Q081Read Burst Marks the Third Beat as Last
- Q088FIFO Count Changes on Simultaneous Push and Pop
- Q093A Single Send Command Produces Two Transfers
- Q099Block Remains in Reset
- Q108Fixed-Priority Arbiter Picks the Wrong Requester
- Q116Read Attempt on an Empty FIFO
- Q125Acknowledge Without an Outstanding Request
- Q131Read Returns Data From the Wrong Register
- Q143Reset Pulse Is Too Short
- Q152Interrupt Pulse Is Missing
- Q167APB Select Drops During a Wait State
- Q180Grant Remains High After Request Ends
- Q189Request Exceeds Its Timeout
- Q201FIFO Full Flag Asserts Late