Q109FreeSystemVerilog
Enforce simplified per-bank command timing
Interview prompt
Question
A four-bank controller accepts or rejects ACT, READ, and PRE commands from one input slot each cycle. Implement the synthesizable bank-state and timing guard. The complete ports, command constants, per-bank declarations, synchronous reset and named combinational/sequential hooks are supplied. Input command controls are known and stable before each rising edge. Equivalent timestamp or bounded cooldown implementations are acceptable; only accepted events reload timing windows, while elapsed time advances on all active clocks.
Candidate starting point
Implementation scaffold
module bank_timing_guard (
input logic clk,
input logic rst_n,
input logic cmd_valid,
input logic [1:0] cmd,
input logic [1:0] bank,
output logic accept,
output logic reject
);
localparam logic [1:0] ACT = 2'd0, READ = 2'd1, PRE = 2'd2;
logic [3:0] open;
logic [3:0] read_seen;
logic [1:0] read_block [4];
logic pre_block [4];
logic act_block [4];
integer i;
always_comb begin : decide_command
// Implement here: pre-edge legality and mutually exclusive accept/reject.
end
always_ff @(posedge clk) begin : update_bank_timing
if (!rst_n) begin
open <= 0;
read_seen <= 0;
for (i = 0; i < 4; i++) begin
read_block[i] <= 0;
pre_block[i] <= 0;
act_block[i] <= 0;
end
end else begin
for (i = 0; i < 4; i++) begin
// Implement here: elapsed cooldown advancement for each bank.
end
if (accept) begin
case (cmd)
ACT: begin
// Implement here: accepted ACT state and READ window.
end
READ: begin
// Implement here: accepted READ state and PRE window.
end
PRE: begin
// Implement here: accepted PRE state and ACT window.
end
default: ;
endcase
end
end
end
endmodule
Reviewed example
Trace one case
Input
Accept ACT bank0 at C0, then present READ bank0 at C2 and again at C3.Expected output
The C2 READ is rejected and the C3 READ is accepted.The ACT-to-READ guard requires three full cycles after C0, so the bank's read cooldown expires only for the C3 command.
What to cover
Requirements
- After reset all banks are closed and an ACT is immediately legal. accept and reject are combinational functions of cmd_valid, cmd, bank, and registered pre-edge bank/timestamp state; both are 0 when cmd_valid=0, and cmd_valid=1 with cmd=3 gives accept=0 and reject=1.
- ACT is legal only for a closed bank and at least two full cycles after its last accepted PRE; READ is legal only for an open bank and at least three full cycles after its accepted ACT.
- PRE is legal only for an open bank and at least two full cycles after its most recent accepted READ; if no READ occurred since ACT, PRE is legal immediately.
- On a rising edge, update bank open/closed state and reload command timing windows only for pre-edge accept=1. Rejected/idle/invalid commands do not reload event state; elapsed-time counters still advance each active clock. rst_n=0 has priority and resets all banks.