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Hardware interview practice

End run phase with a forever monitor

MediumUVM ComponentsSystemVerilog

A test owns finite traffic and also starts a forever monitor in run_phase. Show how the test ends without waiting for the monitor to return.

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Starting point

Question code

task run_phase(uvm_phase phase);
Reviewed example

Work through one case

Input
traffic completes, the last objection drops, and no new objection is raised during drain time
Expected output
run phase ends; the forever monitor is terminated; later phases run

The forever process belongs to the task phase and does not prevent phase completion after objections and drain handling finish.

What to cover

Requirements

  1. Raise the objection before starting finite traffic.
  2. Drop it only after all test-owned traffic completes.
  3. Explain what happens to forever processes spawned by the task phase.
  4. State the default effect of UVM's finish_on_completion setting.
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