Q135FreeSystemVerilog
Verify duplicate token supply
Question
Verify a command-admission block that decides whether a stock list contains enough copies of every requested 4-bit token. Complete the supplied checker module; MAX_LATENCY is positive. Inputs are interpreted at rising-edge samples before that edge's nonblocking updates; the harness drives them before the edge. Sample reset low before the first request. Reset, start, busy, and done are known at sampled edges; lengths are known at acceptance; only active entries with legal lengths must be known. Unused suffix values and all entries under illegal lengths are ignored. An accepted request is start && !busy. Its completion must be sampled 1 through MAX_LATENCY edges later, inclusive; a missing completion reports on the next edge. Completion is processed before a same-edge new acceptance. Adjacent high done samples are legal when they retire distinct previously accepted requests; a request cannot complete twice or complete on its own accepting edge. Busy-time starts do not change the pending prediction. Reset cancels pending ownership and age. The supplied diagnostic helper accumulates reports across resets.
Implementation scaffold
module token_supply_checker #(parameter int MAX_LATENCY = 70) (
input logic clk, rst_n, start,
input logic [5:0] request_len, stock_len,
input logic [3:0] request_token [32], stock_token [32],
input logic busy, done, request_error, can_supply
);
bit pending = 0;
int unsigned age = 0;
bit expected_error;
int unsigned errors = 0;
// Supplied diagnostics; reports accumulate across sampled resets.
function void report_error(string message);
if (errors != '1) errors++;
$error("%s", message);
endfunction
function int unsigned error_count(); return errors; endfunction
initial begin
if (MAX_LATENCY <= 0) $fatal(1, "MAX_LATENCY must be positive");
end
bit expected_supply;
function automatic bit tokens_available(
input logic [3:0] request[32], input int unsigned request_count,
input logic [3:0] stock[32], input int unsigned stock_count
);
// TODO: build fresh histograms and compare multiplicities; reject bad lengths.
endfunction
task automatic check_sample();
// TODO: predict at acceptance and check reset, ownership, outputs and deadline.
endtask
always @(posedge clk) check_sample();
endmodule
Trace one case
request tokens=[2,2,5]; stock tokens=[2,5,2,7]can_supply=1Fresh histograms count demand token 2 twice and token 5 once, both no greater than their stock multiplicities.
Requirements
- For legal lengths 0 through 32, count only active entries in fresh 16-bin histograms.
- Return true exactly when every requested count is no greater than the stock count; an empty request is true.
- Illegal lengths return request_error with can_supply zero, and inactive suffix entries never affect prediction.
- On accepted START, compute and retain the complete error/value prediction. Require each request to complete once within 1..MAX_LATENCY sampled edges; report missing completion on the following edge. Reset cancels ownership. Report any later completion without a new owner as an error.