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Hardware interview practice

Code an asynchronously reset register with enable

EasyRTL DesignSystemVerilog

Write parameterized RTL for a register that samples data when enable is high, holds its value otherwise, and asserts reset asynchronously low.

Starting point

Question code

module enabled_register #(
  parameter int W = 8
) (
  input  logic         clk,
  input  logic         rst_n,
  input  logic         en,
  input  logic [W-1:0] d,
  output logic [W-1:0] q
);
Reviewed example

Work through one case

Input
W=8; rst_n=1, en=1, d=8'h5A at a rising clock edge
Expected output
q=8'h5A after the nonblocking update

With reset inactive and enable asserted, the edge samples d into q. If enable were low, q would retain its prior value.

What to cover

Requirements

  1. Assert reset on negedge rst_n without waiting for a clock edge.
  2. Model normal reset release behavior at the next posedge clk.
  3. Hold q when en is low.
  4. Use nonblocking assignments for q.
Continue practicing
RTL DesignCompare synchronous and asynchronous resetRTL DesignRegister a glitch-free decoded enableReset DesignSynchronize reset release in each clock domain