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Q156FreeSystemVerilog

Build one-write/two-read memory from BRAM

Difficulty
Medium
Topic
RTL Design
Language
SV
Interview prompt

Question

Two identical synchronous 1W1R BRAMs must implement a logical memory with one write and two independent reads. Implement the mirrored SystemVerilog wrapper with defined collision behavior.

Candidate starting point

Implementation scaffold

module mirrored_1w2r_memory (
  input  logic        clk,
  input  logic        we,
  input  logic [7:0]  waddr,
  input  logic [7:0]  raddr0,
  input  logic [7:0]  raddr1,
  input  logic [31:0] wdata,
  output logic [31:0] rdata0,
  output logic [31:0] rdata1
);
  logic [31:0] mem0 [0:255];
  logic [31:0] mem1 [0:255];

  always_ff @(posedge clk) begin : mirrored_write_and_registered_reads
    // TODO: broadcast each write and implement independent write-first read results.
  end
endmodule
Reviewed example

Trace one case

Input
Write address 5 with 32'h0000_00AA, then issue reads of address 5 on both read ports.
Expected output
One edge after the reads, rdata0=rdata1=32'h0000_00AA.

The write is mirrored into both BRAM copies, and each registered read port retrieves the same defined logical location.

What to cover

Requirements

  1. Instantiate or infer two 256x32 1W1R memories and apply every write to both copies on the same rising edge.
  2. Use copy 0 for read address raddr0 and copy 1 for raddr1; both read outputs are registered with one-cycle latency.
  3. Define same-edge read/write to the same address as write-first, returning wdata on the matching read output.
  4. There is no reset for memory contents or read data; the testbench compares read outputs only after a defined location is written.
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