Hardware interview practice

Verify a retained-memory water accelerator

HardReference ModelsSystemVerilog

Write the water oracle and register checks for an accelerator whose retained static RAM (SRAM) stores elevations and whose control registers respond in exactly two cycles.

Starting point

Question code

interface rain_if(input logic clk);
  logic rst_n, cfg_valid, cfg_ready, cfg_write;
  logic [9:0] cfg_addr;
  logic [31:0] cfg_wdata, cfg_rdata;
  logic cfg_rsp_valid, cfg_rsp_ready, cfg_rsp_err;
  logic result_valid, result_ready, result_error;
  logic [19:0] total_water;
  logic [11:0] peak_water;
  logic [5:0] peak_index;
endinterface

Reviewed example

Work through one case

Input

LEN=5; retained HEIGHT=[0,2,0,2,0]

Expected output

total_water=2; largest_per_index=2; peak_index=2

Only the center valley traps water, and the retained SRAM contents survive control reset semantics.

What to cover

Requirements

Model one pending register request with a response exactly two cycles later and stable fields under response backpressure.
For legal lengths, cross-check an O(N squared) scan against prefix/suffix maxima; preserve the total and break peak ties toward the lowest index.
A bad length produces one zeroed error result; busy writes have no state effect, and valid results meet the 3 times LEN plus 12 bound.
Reset cancels register and job responses and clears control state while retaining the complete HEIGHT memory model.