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Q162FreeSystemVerilog

Reverse a physical bus at the lane boundary

Difficulty
Easy
Topic
RTL Design
Language
SV
Interview prompt

Question

A board routes a peripheral bus in reverse bit order. Build a parameterized combinational adapter whose output bit i is input bit W - 1 - i.

Candidate starting point

Implementation scaffold

module bit_reverse_adapter #(
  parameter int unsigned W = 32
) (
  input  logic [W-1:0] in_bus,
  output logic [W-1:0] out_bus
);
  always_comb begin : reverse_bits
    // TODO: Implement reverse_bits using the supplied state and interface.
  end
endmodule
Reviewed example

Trace one case

Input
W=8; input=8'b1101_0010
Expected output
output=8'b0100_1011

Output bit i is wired directly from input bit 7-i, making this a bit reversal rather than a byte-endian conversion.

What to cover

Requirements

  1. Treat this as bit reversal, not a byte swap or numeric endian conversion.
  2. Support every static width W >= 1, including odd widths and W = 1.
  3. Drive every output bit on every evaluation and infer no state.
  4. Use only compile-time-bounded, synthesizable wiring.
Continue practicing
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