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FIFO Full Flag Asserts Late

EasyWaveform DebuggingSystemVerilog

The FIFO depth is four. occupancy is the number of entries immediately after each edge, and full is the flag observed with that occupancy. Rule to apply: full must be 1 exactly when occupancy equals four, and must be 0 when occupancy is below four. Which full-flag assertion fails first?

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Waveform for FIFO Full Flag Asserts Late. Signals: push, pop, occupancy, full. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. push must remain high after the FIFO becomes full.
  2. B. full must rise when occupancy first becomes one.
  3. C. occupancy may never equal the FIFO depth.
  4. D. full must be high whenever occupancy is four.
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Related questions

Waveform DebuggingRead Attempt on an Empty FIFO→Waveform DebuggingFIFO Count Changes on Simultaneous Push and Pop→Waveform DebuggingFIFO Returns the Wrong Head Entry→
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