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Hardware interview practice

Count active lanes in a predicate mask

EasyRTL DesignSystemVerilog

Implement a combinational population-count unit for a statically sized predicate mask. The result must represent every value from zero through WIDTH.

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Reviewed example

Work through one case

Input
WIDTH=5; predicate mask=5'b10111
Expected output
count=3'b100 (4 active lanes)

$clog2(5+1)=3 result bits represent the all-active value five without truncating the four counted ones.

What to cover

Requirements

  1. Support any static WIDTH >= 1, including non-powers of two.
  2. Size the result with $clog2(WIDTH + 1) so the all-ones answer is representable.
  3. Do not use a simulation-only system task as the implementation.
  4. Assign the accumulator on every evaluation and avoid truncated intermediate results.
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