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Q168FreeSystemVerilog

Count active lanes in a predicate mask

Difficulty
Easy
Topic
RTL Design
Language
SV
Interview prompt

Question

Implement a combinational population-count unit for a statically sized predicate mask. The result must represent every value from zero through WIDTH.

Candidate starting point

Implementation scaffold

module population_count #(
  parameter int unsigned WIDTH = 64,
  localparam int unsigned COUNT_W = $clog2(64'(WIDTH) + 64'd1)
) (
  input  logic [WIDTH-1:0] mask,
  output logic [COUNT_W-1:0] ones
);
  always_comb begin : count_bits
    // TODO: Implement count_bits using the supplied state and interface.
  end
endmodule
Reviewed example

Trace one case

Input
WIDTH=5; predicate mask=5'b10111
Expected output
count=3'b100 (4 active lanes)

$clog2(5+1)=3 result bits represent the all-active value five without truncating the four counted ones.

What to cover

Requirements

  1. Support any static WIDTH >= 1, including non-powers of two.
  2. Size the result with the mathematical ceil(log2(WIDTH + 1)) so the all-ones answer is representable; widen WIDTH before the addition in the parameter expression.
  3. Do not use a simulation-only system task as the implementation.
  4. Assign the accumulator on every evaluation and avoid truncated intermediate results.
Continue practicing
Q1039 · RTL DesignPreserve width through dependent additionsEasyPQ073 · RTL DatapathsDeduplicate a sorted register bankMedium