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Q186FreeSystemVerilog

Detect nonoverlapping 10110 sequences

Difficulty
Medium
Topic
Sequential RTL
Language
SV
Interview prompt

Question

Design a serial sequence detector that accepts one bit per clock and emits a one-cycle pulse when 10110 completes. Bits consumed by a match cannot begin the next match.

Candidate starting point

Implementation scaffold

module sequence_detector (
  input logic clk, rst_n, bit_in,
  output logic detected
);
  typedef enum logic [2:0] {S0, S1, S10, S101, S1011} state_t;
  state_t state;

  always_ff @(posedge clk or negedge rst_n) begin : update_prefix_and_pulse
    // Implement here: reset, prefix advance/fallback and a nonoverlapping pulse.
  end
endmodule
Reviewed example

Trace one case

Input
bit_in at successive rising edges = 1, 0, 1, 1, 0
Expected output
detected = 0, 0, 0, 0, 1

The fifth sampled bit completes 10110, so the registered output pulses for the following cycle and the FSM returns to its no-prefix state.

What to cover

Requirements

  1. Recognize the exact five-bit pattern 10110 without overlap.
  2. Pulse detected for exactly one destination clock cycle.
  3. Clear all partial-match state on reset.
  4. Retain the longest useful suffix after every mismatch, but return to the start state after a full match.
Continue practicing
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