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Hardware interview practice

Merge two sorted ready/valid streams

HardStreaming RTLSystemVerilog

Merge two nonempty finite streams of nondecreasing 16-bit values into one ordered ready/valid stream. Preserve duplicates and choose stream A first when both head values are equal.

Reviewed example

Work through one case

Input
stream A=[1,3,3]; stream B=[2,3]
Expected output
accepted output=[1(A),2(B),3(A),3(A),3(B)]; last=1 only on final B

Equal heads select A one beat at a time, preserving both duplicates and consuming exactly one stream per output handshake.

What to cover

Requirements

  1. Buffer only the current head of each input stream.
  2. Require at least one accepted item on each input; this data-plus-last interface does not encode an empty frame.
  3. Consume exactly one input for each accepted output and never discard both heads on a tie.
  4. Hold output valid, data, and last stable while the consumer stalls.
  5. Assert out_last only on the final item after both input streams have ended.
Continue practicing
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