Q073FreeSystemVerilog
Deduplicate a sorted register bank
Interview prompt
Question
Given a sorted active prefix of a bounded tag array, emit one copy of each adjacent run, report the unique count, and zero the unused output suffix. Assume static N >= 1 and TAG_W >= 1.
Candidate starting point
Implementation scaffold
module sorted_bank_deduplicator #(
parameter int N = 8,
parameter int TAG_W = 10,
localparam int COUNT_W = (N < 1) ? 1 : $clog2(N + 1)
) (
input logic clk,
input logic rst_n,
input logic start,
output logic start_ready,
input logic [COUNT_W-1:0] in_count,
input logic [TAG_W-1:0] tag_in [N],
output logic done,
output logic count_error,
output logic [COUNT_W-1:0] out_count,
output logic [TAG_W-1:0] tag_out [N]
);
logic pending;
logic [COUNT_W-1:0] count_q;
logic count_valid_q;
logic [TAG_W-1:0] tag_q [N];
assign start_ready = !pending;
always_ff @(posedge clk) begin : dedup_proc
int unsigned unique_count;
logic [TAG_W-1:0] previous;
// TODO: Implement dedup_proc using the supplied state and interface.
end
endmodule
Reviewed example
Trace one case
Input
in_count=6; sorted active prefix=[1,1,2,2,2,5]Expected output
N=8; out_count=3; tag_out=[1,2,5,0,0,0,0,0]; count_error=0 when done=1.One value is retained from each adjacent run and the unused bounded suffix is deterministically zeroed.
What to cover
Requirements
- Support an active count from zero through N, including both endpoints.
- Read only entries below in_count and preserve sorted order.
- Keep exactly one copy of each repeated run.
- Accept start only when start_ready is high; reject in_count greater than N with count_error.
- Capture inputs on an accepted start and publish the result on the following edge with a one-cycle done pulse. For an invalid count, assert count_error and return out_count=0 with every output slot zero.