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Hardware interview practice

APB Select Drops During a Wait State

MediumWaveform DebuggingSystemVerilog

An APB access begins at C2. PREADY remains low for two wait-state cycles and rises at C4 to complete the transfer. Rule to apply: During an access with PENABLE=1 and PREADY=0, PSEL, PENABLE, PADDR, and write data must remain stable until the completion edge. Which APB stability assertion fails first?

Waveform for APB Select Drops During a Wait State. Signals: PSEL, PENABLE, PREADY, PADDR. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. PSEL must remain high throughout an access wait state.
  2. B. PREADY must never be low for two cycles.
  3. C. PENABLE must drop whenever PREADY is low.
  4. D. PADDR must change on every wait-state cycle.