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Hardware interview practice

Separate related-clock timing from asynchronous CDC

EasyClock and Reset DomainsSystemVerilog

Clock A and clock B are generated by one PLL with a fixed 2:1 ratio and documented phase. Clock C comes from an independent crystal oscillator. How should crossings be treated?

Choose one

Answer choices

  1. A. Declare all three clocks false paths so no timing or CDC analysis is needed.
  2. B. Time A-to-B as related generated clocks using their known edge relationship; treat crossings to or from C as asynchronous and use an appropriate CDC protocol.
  3. C. Treat A and B as asynchronous because their frequencies differ, and time C as related because all clocks are on the same chip.
  4. D. Use two-flop synchronizers for every A-to-B data bit and ordinary setup timing for C crossings.
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