Q018FreeDesign Verification
SystemVerilog Basic Constraint Interview Question
Question
Which set exactly describes all possible values of x after a successful randomize()?
Code to inspect
class C;
rand int unsigned x;
constraint c { x inside {[1:4]}; x != 3; }
endclassAnswer choices
- A. {1, 2, 4}
- B. {0, 1, 2, 4}
- C. {1, 2, 3, 4}
- D. All unsigned integers except 3
Short answer
The attainable set is `{1, 2, 4}`. Both expressions in the constraint block must hold: membership limits `x` to the inclusive interval 1–4, and the inequality then removes 3. Declaring `x` unsigned does not reintroduce zero.
Why this reasoning works
SystemVerilog treats separate expressions in a constraint block as simultaneous requirements unless their syntax says otherwise. The `inside` expression admits the four integers from 1 through 4. Applying `x != 3` to those candidates filters out only 3, so a successful solve may select 1, 2, or 4.
The `int unsigned` declaration defines the variable’s full underlying domain, but that larger domain does not expand the values permitted by `inside`. Production testbench code should still inspect or assert the return value from `randomize()`, because later additions can make the complete constraint set unsatisfiable even though this small example has legal values.
Interview takeaways
- Constraint expressions apply together
- `inside` narrows the domain
- Check `randomize()` success