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Hardware interview practice

Route a shared read bus without internal tri-states

MediumRTL DesignSystemVerilog

Design a two-master, one-slave read-bus multiplexer. An external sel chooses the eligible master, only one request may be outstanding, and the response must return to the master that launched it. Add a master BFM read task.

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Reviewed example

Work through one case

Input
cycle1 sel=0 and master0 request A handshakes; sel changes to 1 before slave response A at cycle4
Expected output
response valid/data route only to master0; master1 response path remains known inactive

The accepted owner is latched with the request, so a later external selection change cannot misroute the delayed response.

What to cover

Requirements

  1. Use valid/ready handshakes on requests and an explicit valid on responses.
  2. Latch the selected owner when the slave accepts a request; sel may change before the response returns.
  3. Drive inactive response paths to known values rather than high impedance.
  4. Apply backpressure while a read is outstanding and keep the BFM request stable until accepted.
  5. The slave response arrives no earlier than the cycle after request acceptance; a zero-latency slave would require an explicit response bypass.
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