Q184FreeSystemVerilog
Shorten a critical path with pipelining
Interview prompt
Question
A four-operand W-bit sum is too slow as one long combinational expression. Re-architect it as a two-stage pipeline that accepts new inputs every cycle and carries a valid bit to the output. W is positive. Input sampled into stage one at C0 updates the output register just after C1 and is visible to a downstream pre-edge sampler at C2.
Candidate starting point
Implementation scaffold
module pipelined_sum4 #(
parameter int unsigned W = 32
) (
input logic clk,
input logic rst_n,
input logic valid_in,
input logic [W-1:0] a, b, c, d,
output logic valid_out,
output logic [W+1:0] sum
);
logic [W:0] ab_q, cd_q;
logic valid_q;
always_ff @(posedge clk or negedge rst_n) begin : pipeline_data_and_valid
// TODO: Implement pipeline_data_and_valid using the supplied state and interface.
end
endmodule
// TODO: Explain the latency increase, one-item-per-cycle steady throughput, width growth and stated sampling edges.
Reviewed example
Trace one case
Input
After reset has cleared the pipeline, hold rst_n=1. With W=8 and valid_in=1, a=200, b=100, c=50 and d=10 are sampled into stage one at C0.Expected output
Just after C0, the partial registers hold 300 and 60. Just after C1, sum=360 and valid_out=1. A downstream pre-edge sampler observes that result at C2.W+1-bit partials and a W+2-bit final sum preserve all carries. The two valid registers align the qualification with the same transaction.
What to cover
Requirements
- Add enough width to preserve the full mathematical sum.
- Register two pairwise partial sums, then register their final sum.
- Accept one transaction per cycle and preserve two-register data/valid alignment with the stated observation timing.
- Explain that latency increases even though throughput can remain one result per cycle.