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Hardware interview practice

Vote across redundant state monitors

EasyRTL DesignSystemVerilog

Sample five redundant multi-bit state codes and return the code that appears at least three times. If no strict majority exists, report an invalid result and return zero.

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Reviewed example

Work through one case

Input
five sampled state codes=[3,5,3,3,5]
Expected output
majority_valid=1; majority_code=3

Three complete codes equal 3, satisfying the strict majority without unsafe per-bit voting.

What to cover

Requirements

  1. Compare complete state codes rather than voting each bit independently.
  2. Require at least three identical entries out of five.
  3. Produce deterministic zero data when the sampled set has no strict majority.
  4. Treat a rising edge of check as one request, sample all five entries together, and pulse done once for the registered result.
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