Skip to question

Q193FreeSystemVerilog

Implement a divide-by-four clock model

Difficulty
Easy
Topic
RTL Design
Language
SV
Interview prompt

Question

For simulation or FPGA-style RTL, divide clk by four with a resettable two-bit counter. Also state the safe ASIC implementation rule for a generated clock.

Candidate starting point

Implementation scaffold

module clock_div4 (
  input logic clk, rst_n,
  output logic clk_div4
);
  logic [1:0] count;
  always_ff @(posedge clk or negedge rst_n) begin : count_source_edges
    // TODO: clear or increment the two-bit counter.
  end
  always_comb begin : divided_output
    // TODO: drive clk_div4 from the specified counter bit.
  end
  // TODO: state the ASIC generated-clock implementation rule.
endmodule
Reviewed example

Trace one case

Input
Counter starts at 00; apply four rising edges
Expected output
counter: 01,10,11,00; clk_div4: 0,1,1,0

The counter MSB completes one period for every four source-clock periods.

What to cover

Requirements

  1. Clear the two-bit counter with active-low asynchronous reset.
  2. Increment it on every rising edge while reset is inactive.
  3. Drive clk_div4 from counter bit 1 for a 50 percent steady-state duty cycle.
  4. For ASIC clock consumers, require an approved clock-generation primitive and generated-clock constraint.
Continue practicing
Q541 · RTL DesignDivide a 2 MHz clock by twoEasyPQ1054 · RTL DesignGenerate a 50% duty-cycle divide-by-three clockHardPQ690 · RTL DesignHold even decimal counts for an extra enabled cycleMediumPQ740 · TimingGenerate a Divide-by-3 Clock with Equal High and Low TimesMediumPQ972 · TimingTime Two Related FPGA Clock DomainsMediumP