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Hardware interview practice

Implement a divide-by-four clock model

EasyRTL DesignSystemVerilog

For simulation or FPGA-style RTL, divide clk by four with a resettable two-bit counter. Also state the safe ASIC implementation rule for a generated clock.

Starting point

Question code

input logic clk, rst_n;
output logic clk_div4;
Reviewed example

Work through one case

Input
Counter starts at 00; apply four rising edges
Expected output
counter: 01,10,11,00; clk_div4: 0,1,1,0

The counter MSB completes one period for every four source-clock periods.

What to cover

Requirements

  1. Clear the two-bit counter with active-low asynchronous reset.
  2. Increment it on every rising edge while reset is inactive.
  3. Drive clk_div4 from counter bit 1 for a 50 percent steady-state duty cycle.
  4. For ASIC clock consumers, require an approved clock-generation primitive and generated-clock constraint.