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Q149FreeSystemVerilog

Diagnose storage from an incomplete always_comb block

Difficulty
Easy
Topic
RTL Design
Language
SV
Interview prompt

Question

An always_comb block assigns y only when enable is high and has neither a default assignment nor an else branch. What hardware behavior does that incomplete assignment imply?

Provided context

Code to inspect

always_comb begin
  if (enable)
    y = data;
end
Choose one

Answer choices

  1. A. A level-sensitive latch
  2. B. A flip-flop
  3. C. A tri-state output
  4. D. A compile-time constant
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