Skip to question
asic.fyi

Hardware interview practice

Diagnose storage from an incomplete always_comb block

EasyRTL DesignSystemVerilog

An always_comb block assigns y only when enable is high and has neither a default assignment nor an else branch. What hardware behavior does that incomplete assignment imply?

Starting point

Question code

always_comb begin
  if (enable)
    y = data;
end
Choose one

Answer choices

  1. A. A level-sensitive latch
  2. B. A flip-flop
  3. C. A tri-state output
  4. D. A compile-time constant
Continue practicing
RTL DesignReverse a physical bus at the lane boundaryRTL DesignImplement a parameterized binary-to-Gray converterRTL DesignChoose always_comb over a manual sensitivity list