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Clock-Domain Crossing Strategies for ASIC Interviews

MediumClock Domain CrossingOpen ended

Given a single-bit level, a narrow pulse, a slowly changing multi-bit setting, and a sustained data stream, choose an appropriate clock-domain crossing (CDC) architecture and implement representative single-bit level and pulse synchronizers.

Worked case

Example

Input
src_clk: a one-cycle event pulse occurs at t=20 ns
dst_clk: unrelated 7 ns period
Output
The destination observes exactly one event after synchronization; no combinational multi-bit sample is used.

Explanation: A pulse toggle or request/acknowledge synchronizer preserves a brief event across unrelated clocks; a two-flop synchronizer alone is only sufficient for a persistent single-bit level.

Reasoning requirements

  1. Use a two-flop destination synchronizer only for a stable single-bit level.
  2. Transfer a pulse with an acknowledged toggle; the source may issue a pulse only while src_ready is high.
  3. Use a bundled-data handshake for a held multi-bit value and an asynchronous FIFO for a stream.
  4. Use one shared asynchronous reset event, synchronize its release separately in each domain, and initialize both toggle endpoints to zero.

Concise answer

The answer and the key reason

Use a two-flop synchronizer for a stable one-bit level; convert a short pulse into a source toggle and acknowledge it before accepting another event. Hold multi-bit control data stable under a bundled-data handshake, and carry continuous traffic through an asynchronous FIFO. Each destination domain also needs its own reset-release synchronization.

Deeper explanation

Work through the implementation and tradeoffs

The architecture depends on what must survive the crossing. A single stable bit needs metastability containment, but a pulse may disappear between destination edges. Encoding the pulse as a persistent state change makes it observable; returning an acknowledgment supplies explicit backpressure and prevents a second event from overwriting the first.

Synchronizing every bit of a bus independently cannot guarantee a coherent word, because the bits can settle on different destination cycles. A handshake can transfer an infrequently changed bus while the source holds it, whereas an asynchronous FIFO provides storage and rate decoupling for a stream. Resetting toggle endpoints consistently avoids manufacturing a false event.

What to remember

  • Match CDC architecture to traffic
  • Handshake narrow pulses
  • Never bit-sync arbitrary buses

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