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SystemVerilog Packed vs. Unpacked Arrays

EasyData StructuresMultiple choice

How should this declaration be interpreted?

Question code
bit [7:0] bytes [4];

Answer choices

  1. A. One packed 32-bit vector
  2. B. Eight unpacked arrays, each four bits wide
  3. C. Four unpacked elements, each an 8-bit packed vector
  4. D. A dynamic array whose current size is four

Concise answer

The answer and the key reason

Choose C. bytes is an unpacked collection of four elements, and each element is an eight-bit packed vector. The [7:0] dimension appears with the type, so its bits form a contiguous value; [4] follows the identifier and establishes the outer element collection.

Deeper explanation

Work through the implementation and tradeoffs

Packed dimensions appear to the left of the variable name and participate as part of each element’s integral bit representation. That makes bytes[i] an 8-bit value that can be sliced and used in arithmetic. Packed bit numbering here runs from 7 down to 0, so bytes[i][7] selects that element’s most significant bit.

Unpacked dimensions appear after the name and organize separate elements. In this declaration, the outer dimension supplies four byte-sized entries rather than flattening everything into one 32-bit packed vector. The total storage is still 32 bits, but assignment compatibility, indexing order, slicing, and layout semantics differ from a single packed [31:0] declaration.

What to remember

  • Left dimensions are packed
  • Right dimensions are unpacked
  • Four elements, eight bits each

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