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Q016FreeSystemVerilog

SystemVerilog Packed vs. Unpacked Arrays

Difficulty
Easy
Topic
Data Structures
Language
SV
Interview prompt

Question

How should this declaration be interpreted?

SystemVerilog packed vector shown as one contiguous eight-bit row and an unpacked array shown as four separate eight-bit elements.
Packed dimensions form contiguous bits of one vector; unpacked dimensions form separately indexed elements.
Provided context

Code to inspect

bit [7:0] bytes [4];
Choose one

Answer choices

  1. A. One packed 32-bit vector
  2. B. Eight unpacked arrays, each four bits wide
  3. C. Four unpacked elements, each an 8-bit packed vector
  4. D. A dynamic array whose current size is four
Answer framework

Short answer

Choose C. bytes is an unpacked collection of four elements, and each element is an eight-bit packed vector. The [7:0] dimension appears with the type, so its bits form a contiguous value; [4] follows the identifier and establishes the outer element collection.

Why this reasoning works

Packed dimensions appear to the left of the variable name and participate as part of each element’s integral bit representation. That makes bytes[i] an 8-bit value that can be sliced and used in arithmetic. Packed bit numbering here runs from 7 down to 0, so bytes[i][7] selects that element’s most significant bit.

Unpacked dimensions appear after the name and organize separate elements. In this declaration, the outer dimension supplies four byte-sized entries rather than flattening everything into one 32-bit packed vector. The total storage is still 32 bits, but assignment compatibility, indexing order, slicing, and layout semantics differ from a single packed [31:0] declaration.

Interview takeaways

  • Left dimensions are packed
  • Right dimensions are unpacked
  • Four elements, eight bits each
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