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Hardware interview practice

Pipeline a parameterized barrel rotator

HardRTL DesignSystemVerilog

Design a fully parameterized left/right barrel rotator split across two registered stages. Pipeline valid with the data and write a BFM that predicts rotations and checks the fixed latency.

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Reviewed example

Work through one case

Input
W=8; accept x=8'b1001_0001, direction=left, shift=3 at cycle0
Expected output
out_valid at cycle2 with 8'b1000_1100

The two registered stages implement rotate-left-three modulo eight and pipeline valid with every data/control slice.

What to cover

Requirements

  1. Support any W greater than zero, including W = 1, and reduce shift amounts modulo W.
  2. Apply lower shift-control bits before the first register and upper bits before the output register.
  3. Pipeline direction, remaining shift bits, and valid alongside data.
  4. The predictor must handle shift zero without evaluating a shift by the full word width.
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