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Hardware interview practice

Compact valid cache-line words in place

MediumRTL DatapathsSystemVerilog

Compact the valid words in a bounded cache-line register bank toward slot zero while preserving order. Clear every vacated valid bit and data slot.

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Reviewed example

Work through one case

Input
valid=5'b10110; data=[dirty,A,B,dirty,C] by slot 0..4
Expected output
valid=5'b00111; data=[A,B,C,0,0]

Compaction reads only original valid slots in order and clears both data and validity in every vacated suffix slot.

What to cover

Requirements

  1. Use the valid bitmap, not the data value, to decide which words to retain.
  2. Preserve the original order of all valid entries.
  3. Replace the internal line state with the compacted result without overwriting unread values.
  4. Provide fixed busy/done behavior and support all-valid and all-invalid lines.
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