SystemVerilog Interview Questions and Answers

Choose D, logic q. logic is a four-state variable, so it can represent 0, 1, X, and Z and may be assigned by a single always_ff process. bit loses unknown information, while wire describes a net and is not the appropriate procedural storage declaration here.

Choose C: the output is x 1. Ordinary equality cannot decide whether vectors containing unknown bits match, so it produces X. Case equality compares X and Z as actual four-state symbols; since both vectors are x1, that comparison produces 1.

Choose C. bytes is an unpacked collection of four elements, and each element is an eight-bit packed vector. The [7:0] dimension appears with the type, so its bits form a contiguous value; [4] follows the identifier and establishes the outer element collection.

Choose D: $display prints D=0 and $strobe prints S=1. The blocking assignment changes a immediately, while the nonblocking assignment schedules its update for the NBA region. $display runs before that scheduled update; $strobe reports later, after the new value has taken effect.

Choose D. always_comb runs once at time zero and automatically responds to values read by the block, including reads performed inside called functions. It is a procedural combinational construct: timing controls are forbidden, and variables it writes are expected to have a single procedural owner.

The attainable set is `{1, 2, 4}`. Both expressions in the constraint block must hold: membership limits `x` to the inclusive interval 1–4, and the inequality then removes 3. Declaring `x` unsigned does not reintroduce zero.

Randomization succeeds with `x` equal to 20. The class range is marked `soft`, so it behaves as a fallback preference. The inline equality is hard; when the two conflict, the solver discards the soft restriction rather than failing or clamping the result.

The intended probability of `x == 2` is `2/7`. In a `:/` range entry, the stated weight belongs to the range as a whole. Splitting six shares among 1, 2, and 3 gives two each; zero contributes one more share.

The ordering leaves the five legal `(a,b)` pairs unchanged, but it raises `P(a=0)` from `1/5` to `1/2`. `solve a before b` chooses between the two legal values of `a` first, then selects a compatible value for `b`.

Use `modport master(output req, input gnt);` and `modport slave(input req, output gnt);`. In each role declaration, `output` identifies what that endpoint produces and `input` identifies what it consumes.

A virtual interface gives the class-based driver a typed reference to an already-elaborated interface instance. Supplying that reference through configuration avoids fixed hierarchical names and lets the same driver connect to different interfaces; the `.master` modport preserves its intended access directions.

`q` is observed at the `#1step` input sampling point immediately preceding each positive edge, whereas assignments to `d` use the clocking event’s zero-skew output slot. This coordinates simulator scheduling for verification code and leaves the synthesized circuit unchanged.

For this one-cycle antecedent, `a |=> b` is cycle-equivalent to `a |-> ##1 b`. Nonoverlapped implication checks the consequent on the sampled edge after `a`; overlapped implication plus an explicit one-cycle delay reaches that same edge.

The pending attempt is canceled as soon as `rst_n` becomes low. It is not counted as a pass or failure and does not wait to resume. `disable iff` acts independently of the assertion’s sampling edge, so reset between edges still aborts it.

It creates four ordinary bins—one apiece for opcode values 0, 1, 2, and 3. The empty brackets request an unsized bin array, which partitions this small value set into individual bins. The default illegal bin handles all other sampled opcode values.