Question 01EasySystemVerilog
SystemVerilog logic, bit, and wire 4-State Types
A signal is assigned only in one always_ff block, and the verification environment must be able to observe X and Z values. Which declaration best matches that intent?
Concise answerChoose D, logic q. logic is a four-state variable, so it can represent 0, 1, X, and Z and may be assigned by a single always_ff process. bit loses unknown information, while wire describes a net and is not the appropriate procedural storage declaration here.
Question 02EasyData Structures
SystemVerilog Packed vs. Unpacked Arrays
How should this declaration be interpreted?
Concise answerChoose C. bytes is an unpacked collection of four elements, and each element is an eight-bit packed vector. The [7:0] dimension appears with the type, so its bits form a contiguous value; [4] follows the identifier and establishes the outer element collection.
Question 03EasySystemVerilog
SystemVerilog Blocking vs. Nonblocking Assignments
What values are printed by display and strobe, in that order?
Concise answerChoose D: $display prints D=0 and $strobe prints S=1. The blocking assignment changes a immediately, while the nonblocking assignment schedules its update for the NBA region. $display runs before that scheduled update; $strobe reports later, after the new value has taken effect.
Question 04EasyConstraints
SystemVerilog Basic Constraint Interview Question
Which set exactly describes all possible values of x after a successful randomize()?
Concise answerThe attainable set is `{1, 2, 4}`. Both expressions in the constraint block must hold: membership limits `x` to the inclusive interval 1–4, and the inequality then removes 3. Declaring `x` unsigned does not reintroduce zero.
Question 05EasyTemporal Checks
SVA Overlapped vs. Nonoverlapped Implication
For the one-cycle antecedent a, which property is cycle-equivalent to the property shown?
Concise answerFor this one-cycle antecedent, `a |=> b` is cycle-equivalent to `a |-> ##1 b`. Nonoverlapped implication checks the consequent on the sampled edge after `a`; overlapped implication plus an explicit one-cycle delay reaches that same edge.
Question 06EasyTemporal Checks
How SVA disable iff Handles Reset
A request is sampled high, but rst_n goes low before the next edge where gnt would be checked. What happens to that pending assertion attempt?
Concise answerThe pending attempt is canceled as soon as `rst_n` becomes low. It is not counted as a pass or failure and does not wait to resume. `disable iff` acts independently of the assertion’s sampling edge, so reset between edges still aborts it.
