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Q049FreeDesign Verification

APB Protocol Monitor without SVA

Difficulty
Medium
Topic
Protocol Checking
Language
SV
Interview prompt

Question

Monitor an Advanced Peripheral Bus (APB) transfer at each rising clock edge and detect setup/access sequencing violations without using assertions.

Starting point

Question code

class ApbMonitor;
  void sample(bit psel, bit penable, bit pready, bit pwrite,
              longint paddr, longint pwdata, int pstrb, bit pslverr);
  int error_count();
endclass
Reviewed example

Trace one case

Input
cycle 0: PSEL=1, PENABLE=0, PADDR=0x40
cycle 1: PSEL=1, PENABLE=1, PREADY=0
cycle 2: PSEL=1, PENABLE=1, PREADY=1
Expected output
one APB transfer completes at cycle 2; address remains 0x40 through the wait state

The setup phase precedes the access phase, and all control fields remain stable while PREADY is low.

What to cover

Requirements

  1. Every access phase must be preceded by a setup phase.
  2. Address, direction, write data, and strobes remain stable while PREADY is low.
  3. PSLVERR is meaningful only on a completing access transfer.
  4. Support legal back-to-back transfers and flag an access that stalls beyond N cycles.
Continue practicing
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