Specification and PPA targets
Translate product intent into measurable behavior, interfaces, latency budgets, throughput targets, and power-performance-area constraints.
- Requirements
- Interface contracts
- PPA budgets
Specification to signoff
ASIC Design Guide
ASIC design turns behavior, performance targets, and physical constraints into manufacturable silicon. This guide connects the decisions made at each stage so that RTL is not treated separately from timing, power, verification, or implementation.
Build a mental model of the complete design flow and understand what each stage must prove before tapeout.
Reviewed and updated July 2026
Coverage map
What this guide covers
Microarchitecture and RTL
Partition behavior into blocks, define pipelines and state, and express the design as deterministic, synthesizable RTL.
- Datapaths and control
- Pipelines
- Ready/valid flow control
Clock, reset, CDC, and power
Engineer safe boundaries between clock and power domains while making reset behavior explicit and verifiable.
- Clock domains
- Reset strategy
- CDC and low-power intent
Synthesis and timing closure
Constrain the real design, inspect synthesis quality, and close setup and hold timing across operating corners.
- SDC constraints
- Static timing analysis
- QoR tradeoffs
Physical design and signoff
Carry logical intent through floorplanning, placement, routing, DFT, extraction, and final signoff checks.
- Floorplan and routing
- DFT
- IR, EM, and equivalence
Apply the concepts
Move from reading to reasoning.
Use the question bank to explain assumptions, debug failures, and validate tradeoffs in the language interviewers expect.