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Hardware interview practice

Detect and recover an upset one-hot FSM

MediumReliable RTLSystemVerilog

Protect a 16-state one-hot control FSM against single-event upsets. Detect zero-hot and multi-hot encodings with shallow logic, force a safe recovery state, and add an assertion for verification.

Reviewed example

Work through one case

Input
16-bit one-hot state=16'b0000_0000_0000_0010; then an upset creates 16'b0000_0000_0000_0110
Expected output
normal next state is 16'b0000_0000_0000_0100; the upset asserts error and the next edge forces SAFE 16'b0000_0000_0000_0001

Two asserted state bits are illegal even though a binary encoding might interpret a flipped bit as another valid state.

What to cover

Requirements

  1. Treat exactly one asserted bit as legal; all-zero and two-or-more-hot values are illegal.
  2. On detection, override normal next-state logic and recover to SAFE on the next edge.
  3. Expose an error indication so the event can be logged or escalated.
  4. Explain why a binary-state bit flip can silently land on another valid code.
Continue practicing
FSMsChoose one-hot or binary FSM encoding