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Q166FreeSystemVerilog

DRAM Bank Timing Checker

Difficulty
Hard
Topic
Timing Models
Language
SV
Interview prompt

Question

Check a simplified dynamic random-access memory (DRAM) command stream against per-bank and global timing rules. Commands carry an explicit cycle number, bank, and row. Use the public timing parameters below, all nonnegative. A command at last+T is legal. The model begins with all banks precharged and permits multiple observations at one cycle. Refresh requires every bank closed and tRP elapsed since any recorded precharge; tRFC and other DRAM timings are outside this model. Use BANKS>=1 and finite nonnegative cycle numbers with enough signed longint range for every last_timestamp + timing_parameter operation; arithmetic overflow is outside this exercise.

Candidate starting point

Implementation scaffold

typedef enum {ACT, READ, WRITE, PRECHARGE, REFRESH} dram_cmd_e;
class DramTimingChecker #(int BANKS = 16);
  typedef struct {
    bit open;
    int row;
    longint last_act;
    longint last_pre;
    bit have_act;
    bit have_pre;
  } bank_state_t;

  bank_state_t banks[BANKS];
  longint act_window[$];
  longint last_cycle, last_global_act;
  bit have_cycle, have_global_act;
  int unsigned errors;
  int tRCD = 4, tRAS = 10, tRP = 4, tRC = 14, tRRD = 4, tFAW = 16;

  function void fail(string message);
    errors++;
    $error("DRAM timing checker: %s", message);
  endfunction

  function bit gap_ok(longint now, longint then, int gap);
    // A command exactly gap cycles later is legal.
    return now >= then + gap;
  endfunction

  function void observe(dram_cmd_e cmd, int bank, int row, longint cycle);
    // TODO: validate timing, report violations, and update accepted state.
  endfunction

  function int error_count(); return errors; endfunction
endclass
Reviewed example

Trace one case

Input
configure tRCD=4 and tRAS=8
t=0 ACT bank0
t=2 READ bank0
t=4 READ bank0
t=7 PRE bank0
t=8 PRE bank0
Expected output
errors at t=2 and t=7; commands at t=4 and t=8 are legal

The timing model checks elapsed cycles against both activation-to-read and minimum-active-time constraints.

What to cover

Requirements

  1. Track open/closed bank state and the active row in every bank.
  2. Enforce tRCD, tRAS, tRP, and tRC with correctly defined inclusive/exclusive boundaries.
  3. Enforce global ACT spacing and the four-activate window (tRRD and tFAW).
  4. Allow refresh only when all banks satisfy the stated precharge requirement.
  5. Reject nonmonotonic cycle observations and continue reporting useful diagnostics after errors.
Continue practicing
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