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Q069FreeSystemVerilog

DRAM Bank Timing Checker

Difficulty
Hard
Topic
Timing Models
Language
SV
Interview prompt

Question

Check a simplified dynamic random-access memory (DRAM) command stream against per-bank and global timing rules. Commands carry an explicit cycle number, bank, and row.

Starting point

Question code

typedef enum {ACT, READ, WRITE, PRECHARGE, REFRESH} dram_cmd_e;
class DramTimingChecker #(int BANKS = 16);
  void observe(dram_cmd_e cmd, int bank, int row, longint cycle);
  int error_count();
endclass
Reviewed example

Trace one case

Input
configure tRCD=4 and tRAS=8
t=0 ACT bank0
t=2 READ bank0
t=4 READ bank0
t=7 PRE bank0
t=8 PRE bank0
Expected output
errors at t=2 and t=7; commands at t=4 and t=8 are legal

The timing model checks elapsed cycles against both activation-to-read and minimum-active-time constraints.

What to cover

Requirements

  1. Track open/closed bank state and the active row in every bank.
  2. Enforce tRCD, tRAS, tRP, and tRC with correctly defined inclusive/exclusive boundaries.
  3. Enforce global ACT spacing and the four-activate window (tRRD and tFAW).
  4. Allow refresh only when all banks satisfy the stated precharge requirement.
  5. Reject nonmonotonic cycle observations and continue reporting useful diagnostics after errors.
Continue practicing
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