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SystemVerilog logic, bit, and wire 4-State Types

EasySystemVerilogMultiple choice

A signal is assigned only in one always_ff block, and the verification environment must be able to observe X and Z values. Which declaration best matches that intent?

Answer choices

  1. A. bit q;
  2. B. int unsigned q;
  3. C. wire q;
  4. D. logic q;

Concise answer

The answer and the key reason

Choose D, logic q. logic is a four-state variable, so it can represent 0, 1, X, and Z and may be assigned by a single always_ff process. bit loses unknown information, while wire describes a net and is not the appropriate procedural storage declaration here.

Deeper explanation

Work through the implementation and tradeoffs

SystemVerilog separates the signal’s value domain from how it is driven. The logic data type retains unknown and high-impedance values, which is important when the verification environment must detect initialization or connectivity problems. In contrast, bit is two-state and coerces away X/Z information, making it unsuitable for this requirement.

An always_ff block models sequential procedural assignment and imposes a single-writer discipline on its left-hand variables. A plain logic declaration expresses that intent directly. A wire is a resolved net intended for structural or continuous driving; although nets are also four-state by default, choosing one here would conflict with the specified procedural ownership rather than clarify it.

What to remember

  • logic preserves X and Z
  • always_ff needs procedural storage
  • wire models a driven net

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