Skip to question
asic.fyi

Hardware interview practice

Block Remains in Reset

EasyWaveform DebuggingSystemVerilog

Each column is one rising clock edge. The top-level reset is released at C2, but block_active remains low through C7 after local synchronization time. Rule to apply: Top-level reset release must reach block_reset_n_sync within two sampled edges. While block_enable=1, block_active must become 1 on the following edge. Therefore a C2 top-level release makes C5 the latest legal block_active assertion. Which signal should be traced next to find out whether reset release reached the block?

Waveform for Block Remains in Reset. Signals: reset_n, block_enable, block_active. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. The AXI write response.
  2. B. The interrupt pending bit.
  3. C. block_reset_n_sync inside the block.
  4. D. The FIFO output data.
Continue practicing
Waveform DebuggingUnknown Output After ResetWaveform DebuggingReset Pulse Is Too ShortWaveform DebuggingSecond Synchronizer Stage Changes Too Soon