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Q099FreeDesign Verification

Block Remains in Reset

Difficulty
Easy
Topic
Waveform Debugging
Language
SV
Interview prompt

Question

Each column shows one rising clock edge. Top-level reset releases at C2, but block_active stays low through C7 despite the allowed local synchronization time. Release must reach block_reset_n_sync within two sampled edges. With block_enable=1, block_active must then become 1 on the following edge, making C5 the latest legal assertion for a C2 release. Which signal would you trace next to check whether reset release reached the block?

Waveform for Block Remains in Reset. Signals: reset_n, block_enable, block_active. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. The AXI write response.
  2. B. The interrupt pending bit.
  3. C. block_reset_n_sync inside the block.
  4. D. The FIFO output data.
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