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Q117FreeSystemVerilog

Model sparse banked memory with packed keys

Difficulty
Medium
Topic
Reference Models
Language
SV
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Question

Build a sparse SystemVerilog memory model addressed by an 8-bit bank and a 16-bit byte offset. Reads must distinguish an unwritten location from a location explicitly written with zero.

Candidate starting point

Implementation scaffold

module sparse_memory_model;
typedef struct packed {
  bit [7:0]  bank;
  bit [15:0] offset;
} addr_t;

bit [31:0] mem[addr_t];

  function automatic void model_write(addr_t addr, bit [31:0] data);
    // TODO: write the exact key.
  endfunction
  function automatic bit [31:0] model_read(addr_t addr, output bit uninitialized_read);
    // TODO: return data and presence status.
  endfunction
  function automatic void model_reset();
    // TODO: flush modeled entries.
  endfunction
endmodule
Reviewed example

Trace one case

Input
write address '{bank:8'h02, offset:16'h0010} with 32'h0000_CAFE, then read the same address
Expected output
data = 32'h0000_CAFE, uninitialized_read = 0

The packed struct forms one stable integral key, so the later lookup finds exactly the previously written bank-and-offset pair.

What to cover

Requirements

  1. Store every valid write at the exact packed address key.
  2. Check exists() before indexing on a read.
  3. Return zero and assert uninitialized_read for an unwritten address.
  4. Delete all associative-array entries on reset or model flush.
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