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asic.fyi

Hardware interview practice

Model sparse banked memory with packed keys

MediumReference ModelsSystemVerilog

Build a sparse SystemVerilog memory model addressed by an 8-bit bank and a 16-bit byte offset. Reads must distinguish an unwritten location from a location explicitly written with zero.

Starting point

Question code

typedef struct packed {
  bit [7:0]  bank;
  bit [15:0] offset;
} addr_t;

bit [31:0] mem[addr_t];
Reviewed example

Work through one case

Input
write address '{bank:8'h02, offset:16'h0010} with 32'h0000_CAFE, then read the same address
Expected output
data = 32'h0000_CAFE, uninitialized_read = 0

The packed struct forms one stable integral key, so the later lookup finds exactly the previously written bank-and-offset pair.

What to cover

Requirements

  1. Store every valid write at the exact packed address key.
  2. Check exists() before indexing on a read.
  3. Return zero and assert uninitialized_read for an unwritten address.
  4. Delete all associative-array entries on reset or model flush.
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