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Q177·Free·SystemVerilog

Implement a parameterized binary-to-Gray converter

Difficulty
Easy
Topic
RTL Design
Language
SV
Interview prompt

Question

Write a synthesizable, parameterized combinational block that converts a binary pointer to Gray code without changing bit order.

Candidate starting point

Implementation scaffold

module bin_to_gray #(
  parameter int W = 4
) (
  input  logic [W-1:0] bin,
  output logic [W-1:0] gray
);
  // TODO: drive gray with the stated combinational conversion.
endmodule
Reviewed example

Trace one case

Input
W=4, bin=4'b1010
Expected output
gray=4'b1111

Shifting 1010 right produces 0101, and 1010 XOR 0101 equals 1111.

What to cover

Requirements

  1. Use one combinational relation with no state.
  2. Support every legal parameter value W >= 1.
  3. Preserve the declared bit order.
  4. State the exact binary-to-Gray relation.
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RTL Synthesis and Proof

Review widths, parameterization, memory inference, pipelining, implementation pressure, and proof evidence.

  • RTL Design
  • SystemVerilog
  • Gray code
  • Combinational logic
RTL Synthesis and Proof →
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