Part 1 · Parallelism and speedup
ILP, pipeline width, and Amdahl’s law
Separate theoretical opportunity from realized throughput, quantify the serial ceiling, and compare deeper, wider, and multicore designs with explicit assumptions.
Parallel work to precise state
Computer Architecture
See how a modern processor finds parallel work, predicts control flow, executes speculatively, and still presents precise sequential behavior.
Compare architectural tradeoffs with explicit performance models and trace the mechanisms that recover correctness when speculation fails.
Updated July 20265 connected chaptersInteractive labs + worked examples
Start Part 1
Part 2 · Out-of-order execution
Rename, schedule, execute, and retire
Trace one instruction through rename, reservation stations, physical registers, the ROB, speculative memory ordering, recovery, and precise retirement.
Part 3 · Branch prediction
Direction, target, history, and recovery
Simulate saturating counters and global history, distinguish BHT direction from BTB targets, and account for bubbles even when direction is correct.
Part 4 · Cache coherence
MSI, MESI, MOESI, and ownership
Track readers, writers, dirty ownership, invalidation, intervention, false sharing, and write-policy consequences across private caches.
Core trace · cycle 184
Speculate wide. Commit in order.
Follow four instructions through prediction, physical-register renaming, readiness-driven execution, branch recovery, and the reorder buffer's precise-state boundary.
Fetch 4 μops/cycleIssue 6-wideBranch I3 mispredictRetire in program order
01 · Front end
Predict + fetch
BTB hit supplies the target before the branch decodes.
- PC
- 0x4000
- Direction
- Taken
Rename + dispatch
New physical names remove WAR and WAW dependencies.
- R1 →
- p21
- ROB
- 48–51
Issue + execute
Independent work passes the older load miss.
I0LSU · L1 missI1ALU · waits p21I2MUL · completeI3BR · redirect
Ready operands choose the lane ↗04 · Visibility gateReorder buffer
Completed values wait until the head is safe to retire.
48 · I049 · I150 · I251 · I3
Head blocked by I0 ↗05 · Architectural stateRetire in order
Only the ROB head may make results externally visible.
- Before I0
- 0 visible
- After ready
- I0 → I3
L1D + memory orderingI0 miss · MSHR 2 allocatedPrivate caches still need a coherent global view ↗
Branch recovery · I3 resolves not taken
Trace prediction and recovery ↗Flush younger μops, restore the rename checkpoint, and redirect fetch. Older I0–I2 remain intact.
Completion order
- 01I2 · MULcycle 188
- 02I3 · BRcycle 189
- 03I0 · LDcycle 196
- 04I1 · ADDcycle 197
I2 and I3 finish while older instructions are still pending.
ROB headPrecise-state gateage wins here
Retirement order
- 01I0 · LDcycle 197
- 02I1 · ADDcycle 198
- 03I2 · MULcycle 198
- 04I3 · BRcycle 198
The machine exposes the original program order, never completion order.
Reasoning checkpoints
Questions worth answering without notes.
Each answer states the mechanism first, then the consequence.01Why does register renaming remove WAR and WAW but not RAW dependencies?+
WAR and WAW are name collisions: separate physical registers give the independent values different destinations. RAW is a real value dependency, so the consumer must still wait until its producer has generated the operand.
02How can a correctly predicted taken branch still create a bubble?+
Correct direction is only half the fetch decision. A missing or late BTB target, an indirect target mismatch, an instruction-cache or TLB miss, or insufficient fetch bandwidth can prevent the front end from delivering target instructions on the next cycle.
03What happens when another core reads a line held in MESI Exclusive state?+
The owner observes the read request and downgrades from Exclusive to Shared. The requester receives a clean copy and also enters Shared; memory remains authoritative because the Exclusive copy was not dirty.
Keep practicing
Move from recognition to explanation.
These links open the existing practice bank without publishing protected solutions on this guide.Continue the system