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From one instruction to many cores
Understand how a processor executes instructions, reaches memory, and makes speculative work safe. Build the model, change its inputs, and explain the tradeoffs.
8 chapters · One learning path
Each chapter has a worked explanation and an experiment. Start at chapter 1, or jump to the problem in front of you.
Put it into practice
Choose a prompt, or follow the chapters to build the model behind it.
Example core trace · cycles 184–198
Follow four instructions through prediction, physical-register renaming, readiness-driven execution, branch recovery, and the reorder buffer's precise-state boundary.
BTB hit supplies the target before the branch decodes.
New physical names remove WAR and WAW dependencies.
Independent work passes the older load miss.
Completed values wait until the head is safe to retire.
Commit register state in order; stores can become visible to other cores later.
Flush younger μops, restore the rename checkpoint, and redirect fetch. Older I0–I2 remain intact.
I2 and I3 finish while older instructions are still pending.
The machine exposes the original program order, never completion order.
Check your understanding
WAR and WAW are name collisions: separate physical registers give the independent values different destinations. RAW is a real value dependency, so the consumer must still wait until its producer has generated the operand.
Correct direction is only half the fetch decision. A missing or late BTB target, an indirect target mismatch, an instruction-cache or TLB miss, or insufficient fetch bandwidth can prevent the front end from delivering target instructions on the next cycle.
The owner observes the read request and downgrades from Exclusive to Shared. The requester also enters Shared. No dirty-owner writeback is needed because the Exclusive copy is clean relative to its backing coherence level; this does not imply that DRAM is current in every multilevel hierarchy.
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