Hardware interview practice

Effect of positive capture-clock skew

EasyTiming & STASystemVerilog

For one register-to-register path, the capture clock arrives later than the launch clock. All other delays are unchanged. What is the usual first-order timing effect of this positive capture skew?

Choose one

Answer choices

A. It helps setup slack but hurts hold slack.
B. It helps both setup and hold slack by the same amount.
C. It changes neither check because skew is ignored by STA.
D. It hurts setup slack but helps hold slack.

Continue practicing

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