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Q146FreeSystemVerilog

Choose Mealy timing for an immediate match

Difficulty
Easy
Topic
RTL Design
Language
SV
Interview prompt

Question

A bit-stream detector stores whether the previous sampled bit was one. At each accepting edge, the receiver samples combinational match and the known, stable bit_in before the history register updates. It must recognize a second consecutive one at that edge. Which output style directly implements the stated timing? The combinational value need not remain unchanged after the history update.

Choose one

Answer choices

  1. A. A combinational output equal only to bit_in, with no state term.
  2. B. A Moore output asserted one cycle after entering a separate matched state.
  3. C. A Mealy output equal to previous_was_one && bit_in.
  4. D. A Moore output that depends only on the no-previous-one state.
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