Skip to question
SystemVerilogDesignVerificationFirmwareArchitectureASIC Interview Questions→
/Interview questions/Measure latency to the next higher sample

Q107·Free·SystemVerilog

Measure latency to the next higher sample

Difficulty
Medium
Topic
Streaming Algorithms
Language
SV
Interview prompt

Question

For every accepted temperature in a bounded trace, compute the distance to the first later sample with a strictly greater value, or zero when no such sample exists.

Candidate starting point

Implementation scaffold

module future_threshold_latency (
  input  logic       clk,
  input  logic       rst_n,
  input  logic       in_valid,
  input  logic       in_last,
  input  logic [7:0] temperature,
  input  logic       out_ready,
  output logic       in_ready,
  output logic       out_valid,
  output logic       out_last,
  output logic [4:0] out_index,
  output logic [5:0] out_distance
);
  typedef enum logic [1:0] {S_INPUT, S_RESOLVE, S_OUTPUT} state_t;
  state_t state_q;

  logic [7:0] stack_temp_q [0:31];
  logic [4:0] stack_index_q [0:31];
  logic [5:0] distance_q [0:31];
  logic [5:0] stack_count_q, frame_count_q;
  logic [4:0] input_index_q, output_index_q;
  logic [7:0] pending_temp_q;
  logic [4:0] pending_index_q;
  logic pending_last_q;
  logic [4:0] top_slot;

  assign top_slot     = stack_count_q - 1'b1;
  assign in_ready     = (state_q == S_INPUT);
  assign out_valid    = (state_q == S_OUTPUT);
  assign out_index    = output_index_q;
  assign out_distance = distance_q[output_index_q];
  assign out_last     = (state_q == S_OUTPUT) &&
                        ({1'b0, output_index_q} + 1'b1 == frame_count_q);

  always_ff @(posedge clk) begin : sample_and_resolve_frame
    // TODO: implement sampled reset; capture one accepted input; resolve at most
    // one stack pop per edge, then push the retained sample; emit/retire the
    // completed frame in index order while holding output across stalls.
  end
endmodule
Reviewed example

Trace one case

Input
temperature frame = [73, 74, 75, 71, 69, 72, 76, 73]
Expected output
distance = [1, 1, 4, 2, 1, 1, 0, 0]

Resolve an index when the first strictly higher later sample arrives. Equal values remain pending on the non-increasing stack.

What to cover

Requirements

  1. Support frames of 1 to 32 unsigned eight-bit temperatures; equal values are not greater.
  2. Use fixed stack and result storage, and serialize multiple pops caused by one new sample.
  3. Do not accept a new sample until all stack work for the retained sample is complete.
  4. Emit results in original index order only after the frame ends.
  5. Hold index, distance, and last stable while output is stalled.
Exact question handoffPractice Q107

Solve it in the question bank, keep your progress, and reveal the reviewed solution when your access allows.

Open in question bank →
Solution accessEach time you open this Solution, one Practice Credit is used; it is not permanently unlocked. Premium Solution content also uses one credit per opening.
Continue learning

RTL Synthesis and Proof

Review widths, parameterization, memory inference, pipelining, implementation pressure, and proof evidence.

  • Streaming Algorithms
  • Monotonic stack
  • Thermal trace
  • Ordered output
RTL Synthesis and Proof →
Continue practicing

Related questions

Q228 · Streaming RTLMeasure the maximum gain in a sample streamHardP→Q237 · DatapathsCompute every product except one channelMediumP→
ASIC.FYI · Learn silicon end to end.info@asic.fyi