Q098FreeDesign Verification
Verify a bounded step-sequence counter
Question
Verify a single-request block that counts ordered sequences of one-step and two-step advances for distances from zero through 24. Supply the oracle and check_sample body in the complete checker module. MAX_LATENCY is positive; step_ways is called only for legal distances 0 through 24. Inputs are interpreted at rising-edge samples before that edge's nonblocking updates; the harness drives them before the edge. Sample reset low before the first request. Reset, start, busy, and done are known at sampled edges; request fields used at acceptance are known. An accepted request is start && !busy. Its completion must be sampled 1 through MAX_LATENCY edges later, inclusive; a missing completion reports on the next edge. Completion is processed before a same-edge new acceptance. Adjacent high done samples are legal when they retire distinct previously accepted requests; a request cannot complete twice or complete on its own accepting edge. Busy-time starts do not change the pending prediction. Reset cancels pending ownership and age. The supplied diagnostic helper accumulates reports across resets.
Implementation scaffold
module step_sequence_checker #(parameter int MAX_LATENCY = 28) (
input logic clk, rst_n, start,
input logic [4:0] steps,
input logic busy, done, request_error,
input logic [31:0] ways
);
bit pending = 0;
int unsigned age = 0;
bit expected_error;
int unsigned errors = 0;
// Supplied diagnostics; reports accumulate across sampled resets.
function void report_error(string message);
if (errors != '1) errors++;
$error("%s", message);
endfunction
function int unsigned error_count(); return errors; endfunction
initial begin
if (MAX_LATENCY <= 0) $fatal(1, "MAX_LATENCY must be positive");
end
logic [31:0] expected_ways;
// Called only with n in 0 through 24.
function automatic longint unsigned step_ways(int unsigned n);
// TODO: compute the bounded recurrence.
endfunction
task automatic predict_steps(
input int unsigned n,
output bit expected_error,
output logic [31:0] expected_ways
);
// TODO: predict the complete error/result pair.
endtask
task automatic check_sample();
// TODO: track acceptance, reset, completion ownership, results, and deadline.
endtask
always @(posedge clk) check_sample();
endmodule
Trace one case
request steps=5; then request steps=25steps 5: ways=8,error=0; steps 25: ways=0,error=1The legal request follows ways(5)=8, while 25 is above the supported bound and returns the defined zeroed error result.
Requirements
- Predict ways(0)=1, ways(1)=1, and ways(n)=ways(n-1)+ways(n-2).
- Return request_error with ways zero for values above 24.
- Snapshot steps on acceptance and require exactly one sampled completion within the bounded latency.
- Ignore busy-time starts and cancel all pending completion obligations on reset.
