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Hardware interview practice

Find the lowest set lane

EasyRTL DesignSystemVerilog

An eight-lane issue block must select the lowest-numbered requested lane. Write a combinational SystemVerilog find-first-set block and a self-checking test loop.

Starting point

Question code

input logic [7:0] req;
output logic valid;
output logic [2:0] index;
Reviewed example

Work through one case

Input
req=8'b0000_0000.
Expected output
valid=0 and index=0.

No lane is requested, so the specified empty-case defaults remain selected.

What to cover

Requirements

  1. If req is nonzero, set valid=1 and index to the smallest i for which req[i]=1.
  2. If req is zero, set valid=0 and index=0.
  3. Use combinational synthesizable RTL and make the priority explicit.
  4. The test code must iterate all 256 request values and compare against an independent loop model.
Continue practicing
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