Q009FreeSystemVerilog
Async Assert, Sync Deassert Reset
Question
Design an active-low reset conditioner with asynchronous assertion and a two-flop synchronized release. In ideal RTL, release follows two destination-clock edges after arst_n rises; physical synchronization can add uncertainty near a sampling aperture. Explain when synchronous and asynchronous reset styles are appropriate.
Implementation scaffold
module reset_sync (
input logic clk,
input logic arst_n,
output logic srst_n
);
(* ASYNC_REG = "TRUE" *) logic [1:0] release_q;
always_ff @(posedge clk or negedge arst_n) begin : release_pipe
// TODO: Implement release_pipe using the supplied state and interface.
end
always_comb begin : conditioned_output
// TODO: Drive srst_n from the second release stage.
end
endmodule
// TODO: Explain reset-style selection, one local conditioner per unrelated domain, physical release checks and selective datapath reset.
Trace one case
arst_n falls between clocks, then rises well away from a destination sampling edge. Observe the ideal RTL after each subsequent rising edge.srst_n falls immediately on assertion. After release, it remains low after the first edge and rises after the second.The two-flop chain confines release to the destination clock domain and reduces metastability risk. Physical safety still requires suitable synchronizer placement, timing constraints and reset distribution; a digital simulation does not prove zero recovery/removal risk.
Requirements
- Asserting arst_n low must force srst_n low without waiting for a clock.
- Deassertion must pass through two flops in the destination domain.
- Instantiate one conditioner per unrelated clock domain.
- Do not claim that every datapath register must be reset; reset control and validity state according to the specification.
Short answer
Clear both stages of a two-flop chain asynchronously when arst_n falls. After arst_n rises, shift a 1 through the chain on destination-clock edges and derive srst_n from the second stage. Instantiate this conditioner separately for every unrelated clock, and reset only state that the design contract requires.
Why this reasoning works
Immediate assertion is useful when the clock may be absent or stopped: the asynchronous clear forces local reset active without waiting. Release is different. If it occurs near a clock edge, recovery or removal timing can be violated, so the first stage may become metastable while the second stage gives it time to resolve before release is observed.
The resulting local reset changes inactive only on a clock edge and remains monotonic once released. A synchronous-reset style is often simpler when the clock is guaranteed and timing closure can cover the reset path. Wide datapaths do not automatically need reset; validity, protocol, and control state usually determine what initialization is essential.
Interview takeaways
- Assert reset asynchronously
- Release reset synchronously
- Condition every clock domain