Hardware interview practice
Async Assert, Sync Deassert Reset
Design an active-low reset conditioner that asserts immediately but releases only after two clean destination-clock edges. Explain when synchronous and asynchronous reset styles are appropriate.
Example
async_reset_n falls between clocks, then rises 1 ns before a destination edgereset_out asserts immediately and deasserts only after two clean destination-clock edgesExplanation: Asynchronous assertion protects the domain immediately, while synchronized release prevents recovery/removal violations at the state elements.
Reasoning requirements
- Asserting arst_n low must force srst_n low without waiting for a clock.
- Deassertion must pass through two flops in the destination domain.
- Instantiate one conditioner per unrelated clock domain.
- Do not claim that every datapath register must be reset; reset control and validity state according to the specification.
Concise answer
The answer and the key reason
Deeper explanation
Work through the implementation and tradeoffs
Immediate assertion is useful when the clock may be absent or stopped: the asynchronous clear forces local reset active without waiting. Release is different. If it occurs near a clock edge, recovery or removal timing can be violated, so the first stage may become metastable while the second stage gives it time to resolve before release is observed.
The resulting local reset changes inactive only on a clock edge and remains monotonic once released. A synchronous-reset style is often simpler when the clock is guaranteed and timing closure can cover the reset path. Wide datapaths do not automatically need reset; validity, protocol, and control state usually determine what initialization is essential.
What to remember
- Assert reset asynchronously
- Release reset synchronously
- Condition every clock domain
Practice the complete prompt