Hardware interview practice
Release reset safely in two clock domains
One active-low reset pin asynchronously resets logic in two unrelated clock domains. Which release strategy best avoids recovery/removal problems in each domain?
Choose one
Answer choices
- A. Deassert reset on whichever clock edge occurs first and rely on static timing to align the domains.
- B. Route the raw asynchronous reset directly to every flip-flop for both assertion and deassertion.
- C. Synchronize reset once in the faster domain and reuse that synchronized reset in every other domain.
- D. Assert reset asynchronously, but deassert it through a separate two-flop reset synchronizer in each clock domain.