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Q105FreeSystemVerilog

Release reset safely in two clock domains

Difficulty
Easy
Topic
CDC & RDC
Language
SV
Interview prompt

Question

One active-low reset pin asynchronously resets logic in two unrelated clock domains. Which release strategy best avoids recovery/removal problems in each domain?

Choose one

Answer choices

  1. A. Deassert reset on whichever clock edge occurs first and rely on static timing to align the domains.
  2. B. Route the raw asynchronous reset directly to every flip-flop for both assertion and deassertion.
  3. C. Synchronize reset once in the faster domain and reuse that synchronized reset in every other domain.
  4. D. Assert reset asynchronously, but deassert it through a separate two-flop reset synchronizer in each clock domain.
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