Q112FreeSystemVerilog

Multi-Domain Reset Sequencing Monitor

Difficulty: Hard
Topic: Clock and Reset
Language: SV

Interview prompt

Question

Monitor reset assertion and release for fabric, cache, and core domains. Global reset assertion is asynchronous, but each local reset must be released in a controlled order. Sample on an always-on observation clock. Configure positive lock_cycles and min_separation and nonnegative assertion_bound. Number observations after on_global_assert() starting at 1: all local resets must be low by observation N when assertion_bound=N; bound 0 means the first observable sample because the assertion callback has no local-reset arguments. A late assertion reports once. The caller holds PLL qualification inactive until global reset has been deasserted; this API cannot observe a still-held global reset level. Assume each local reset stays low until its one ordered release.

Candidate starting point

Implementation scaffold

class ResetSequenceMonitor;
  typedef enum { WAIT_LOCK, WAIT_FABRIC, WAIT_CACHE, WAIT_CORE, RUN } state_e;
  state_e state = WAIT_LOCK;
  int unsigned lock_count, assertion_age, separation_age, errors;
  int unsigned lock_cycles = 4;
  int unsigned min_separation = 2;
  int unsigned assertion_bound = 2;
  bit assertion_pending, assertion_reported;
  bit prev_fabric_n, prev_cache_n, prev_core_n;

  function void fail(string message);
    errors++;
    $error("reset-sequence monitor: %s", message);
  endfunction

  function void on_global_assert();
    // TODO: implement the stated behavior.
  endfunction
  function void sample(bit pll_lock, bit fabric_rst_n, bit cache_rst_n, bit core_rst_n, bit fabric_active, bit cache_active, bit core_active);
    // TODO: implement the stated behavior.
  endfunction
  function int error_count(); return errors; endfunction
endclass

Reviewed example

Trace one case

Input

assert global reset and all local resets; hold PLL lock high for 4 samples; release fabric reset; wait 2 samples; release cache reset; wait 2 samples; release core reset

Expected output

state sequence: WAIT_LOCK -> WAIT_FABRIC -> WAIT_CACHE -> WAIT_CORE -> RUN; no sequencing error

Four consecutive lock samples qualify release, and the two-sample separation is enforced between fabric, cache, and core reset deassertions.

What to cover

Requirements

All local resets assert within the stated observation bound after global reset.
The phase-locked loop (PLL) lock signal must remain high for M complete samples before any local release.
Release order is fabric, then cache, then core, with configurable minimum separation.
No domain may report functional activity while its reset is asserted.

Continue practicing

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class ResetSequenceMonitor; typedef enum { WAIT_LOCK, WAIT_FABRIC, WAIT_CACHE, WAIT_CORE, RUN } state_e; state_e state = WAIT_LOCK; int unsigned lock_count, assertion_age, separation_age, errors; int unsigned lock_cycles = 4; int unsigned min_separation = 2; int unsigned assertion_bound = 2; bit assertion_pending, assertion_reported; bit prev_fabric_n, prev_cache_n, prev_core_n; function void fail(string message); errors++; $error("reset-sequence monitor: %s", message); endfunction function void on_global_assert(); // TODO: implement the stated behavior. endfunction function void sample(bit pll_lock, bit fabric_rst_n, bit cache_rst_n, bit core_rst_n, bit fabric_active, bit cache_active, bit core_active); // TODO: implement the stated behavior. endfunction function int error_count(); return errors; endfunction endclass

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Implementation scaffold

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