Q197FreeDesign Verification
Monitor an independently stalled binary adder
Question
Verify a serial adder whose A and B operand frames handshake independently and whose least-significant-bit-first (LSB-first) sum frame can stall. Reconstruct accepted operands and check every accepted output bit and last marker. MAX_BITS is from 1 through 32, default 32. Each operand contains 1 through MAX_BITS known LSB-first bits. Sample all channels and active-low reset at posedge clk. Once both operand frames close, the first sum_valid must be sampled on that edge or within MAX_BITS+2 further clock edges, regardless of sum_ready. The base DUT owns the pair through acceptance of its final sum bit: a next operand may first be accepted on a later edge. Reset cancels partial operands and pending output. End the test only after all non-canceled operands and expected output bits complete.
Implementation scaffold
module serial_adder_checker #(parameter int unsigned MAX_BITS = 32) (
input logic clk, rst_n,
input logic a_valid, a_ready, a_last, a_bit,
input logic b_valid, b_ready, b_last, b_bit,
input logic sum_valid, sum_ready, sum_bit, sum_last
);
initial assert (MAX_BITS inside {[1:32]})
else $fatal(1, "MAX_BITS must be from 1 through 32");
logic [31:0] a_value, b_value;
int unsigned a_len, b_len;
bit a_done, b_done, pair_built;
bit awaiting_first_sum;
int unsigned first_sum_cycles_left;
bit expected_bits[$];
task automatic build_sum_frame;
// TODO: construct expected bits and start the first-response deadline.
endtask
always @(posedge clk) begin : sample_transaction
// TODO: sample operands, track the deadline, compare output, and handle reset.
end
property p_sum_stable;
// TODO: Sampled-reset-disabled valid, bit and last stability through acceptance.
endproperty
a_sum_stable: assert property (p_sum_stable);
final begin : check_finished
// TODO: Reject remaining operand fragments, a built pair, expected bits or a pending deadline.
end
endmoduleTrace one case
A=3 arrives LSB-first as [1,1]; B=1 arrives independently as [1]; output ready stalls after its first beatexpected sum bits=[0,0,1] with last only on the third accepted bit3+1=4 requires the final carry bit; independent operand handshakes and the output stall do not advance any unsampled index.
Requirements
- Advance each operand's bit index only on that channel's valid-ready handshake and close a frame only when its last bit is accepted.
- Pair completed A and B frames in order and predict max(length A, length B) bits plus a final bit only when carry remains.
- Compare sum bits only on accepted output transfers and require sum_last exactly on the final expected bit.
- Reject overlength, nested, or next-frame traffic while the base DUT still owns a pair.
- Flush partial operands and expectations on reset and require stalled output data and framing to remain stable.