Q014FreeSystemVerilog
Register a glitch-free decoded enable
Interview prompt
Question
Generate valid when a two-bit input equals 01 or 10. The signal will control downstream sequential logic, so make the decoded result cycle-aligned and glitch-free rather than using it to gate a clock. Treat a as a known synchronous input that meets setup and hold around the sampling edge.
Candidate starting point
Implementation scaffold
module registered_valid_decode (
input logic clk,
input logic rst_n,
input logic [1:0] a,
output logic valid
);
always_ff @(posedge clk or negedge rst_n) begin : register_decoded_enable
// TODO: Implement register_decoded_enable using the supplied state and interface.
end
endmodule
Reviewed example
Trace one case
Input
After reset, inputs a immediately before four rising edges are 00, 01, 11, 10.Expected output
The valid register immediately after those same edges is 0, 1, 0, 1; downstream sequential logic samples those values one edge later.The decode drives a register’s D input, not its clock. Between-edge changes of a cannot change the valid register; asserting rst_n low still clears it asynchronously.
What to cover
Requirements
- Register valid on the functional clock.
- Never create a derived clock with combinational decode logic.
- Reset valid to a known inactive value.
- After a rising edge, valid reflects the input sampled at that edge. A downstream register observes it on the next edge. Only asynchronous reset assertion may change valid between functional clock edges.