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Hardware interview practice

Register a glitch-free decoded enable

EasyRTL DesignSystemVerilog

Generate valid when a two-bit input equals 01 or 10. The signal will control downstream sequential logic, so make the decoded result cycle-aligned and glitch-free rather than using it to gate a clock.

Reviewed example

Work through one case

Input
two-bit inputs by clock=[00,01,11,10] after reset
Expected output
registered valid one cycle later=[0,1,0,1]

Only 01 and 10 decode true, and registering the decode prevents between-edge input transitions from creating a clock-gating glitch.

What to cover

Requirements

  1. Register valid on the functional clock.
  2. Never create a derived clock with combinational decode logic.
  3. Reset valid to a known inactive value.
  4. State the one-cycle latency introduced by registering the decode.
Continue practicing
RTL DesignCode an asynchronously reset register with enable