Hardware interview practice
Glitch-free clock-gate checks
An integrated clock gate latches enable only while clk is low and forms gclk from clk AND the latched enable. A test override also enables the gate. Verify it with assertions and directed edge cases that catch runt or extra pulses.
Starting point
Question code
input logic clk, rst_n, enable, test_enable;
output logic gclk;Reviewed example
Work through one case
Input
gclk is high; enable falls halfway through the clk high phaseExpected output
gclk stays high until the matching clk falling edge, then remains low on later cycles.The low-transparent enable latch cannot capture the disable until clk is low, so the active pulse completes at full width.
What to cover
Requirements
- Use effective_enable=enable OR test_enable, captured only while clk is low.
- Require every gclk edge to align with the corresponding clk edge and require gclk low whenever clk is low.
- A high-phase enable change must neither create nor cut the current gclk pulse.
- Disable checks in reset and require the reference latched enable to clear during a low phase before re-enabling checks.