Q124FreeSystemVerilog
Glitch-free clock-gate checks
Question
An integrated clock gate latches enable only while clk is low and forms gclk from clk AND the latched enable. A test override also enables the gate. Verify it with assertions and directed edge cases that catch runt or extra pulses. This is a zero-delay digital simulation checker, not an analog minimum-pulse-width or metastability model. Begin with known clocks/reset and reset asserted while clk is low. Clock high and low phases have positive duration on the declared 1 fs grid; every reset pulse also lasts at least one 1 fs tick, and the run fits the time range. Enable/test controls are driven without a race at the latch-closing edge; once checking is armed, unknown settled observed values must fail a named assertion. Use the supplied edge collectors and complete the named latch, reset-epoch and final-deferred assertion hooks.
Implementation scaffold
module clock_gate_checker (
input logic clk, rst_n, enable, test_enable, gclk
);
timeunit 1fs;
timeprecision 1fs;
logic reference_enable;
bit checks_armed = 0;
bit saw_low_reset = 0;
logic previous_reset_n = 1'b1;
time last_clk_rise, last_clk_fall;
time last_gclk_rise, last_gclk_fall;
bit saw_clk_rise, saw_clk_fall, saw_gclk_rise, saw_gclk_fall;
always_latch begin : model_enable_latch
// Implement here: low-transparent effective enable and low-phase reset.
end
always @(clk or rst_n) begin : track_reset_epoch
// Implement here: reset-epoch clearing, actual reset-low/clk-low evidence,
// and arming only after that evidence and reset release.
end
// Supplied edge collection; validity bits avoid uninitialized timestamps.
always @(posedge clk) begin
last_clk_rise = $time;
saw_clk_rise = 1;
end
always @(negedge clk) begin
last_clk_fall = $time;
saw_clk_fall = 1;
end
always @(posedge gclk) begin
last_gclk_rise = $time;
saw_gclk_rise = 1;
end
always @(negedge gclk) begin
last_gclk_fall = $time;
saw_gclk_fall = 1;
end
// always_comb reruns when an observed signal, reference latch or timestamp
// settles. final delays reporting; it does not delay expression evaluation.
always_comb begin : settled_checks
a_known_active_inputs: assert final (
// Implement here: the named settled assertion.
);
a_reference_level: assert final (
// Implement here: the named settled assertion.
);
a_low_phase: assert final (
// Implement here: the named settled assertion.
);
a_rise_alignment: assert final (
// Implement here: the named settled assertion.
);
a_fall_alignment: assert final (
// Implement here: the named settled assertion.
);
end
endmoduleTrace one case
gclk is high; enable falls halfway through the clk high phasegclk stays high until the matching clk falling edge, then remains low on later cycles.The low-transparent enable latch cannot capture the disable until clk is low, so the active pulse completes at full width.
Requirements
- Use effective_enable=enable OR test_enable, captured only while clk is low.
- Require every gclk edge to align with the corresponding clk edge and require gclk low whenever clk is low.
- A high-phase enable change must neither create nor cut the current gclk pulse.
- Disable checks while reset is low. Clear the reference enable only while both reset and clk are low, and remember that actual low-phase reset observation for the current reset epoch. Re-enable only after reset release and that observation. A reset pulse confined to clk high clears prior qualification; an ordinary later low phase with reset already high must not rearm the checker. A later reset that is observed while clk is low permits re-entry.