Skip to question
asic.fyi

Hardware interview practice

Read Attempt on an Empty FIFO

EasyWaveform DebuggingSystemVerilog

At each edge, pop and empty are sampled before the operation. occupancy is the number of stored entries immediately after the edge. Rule to apply: A pop is legal only when empty is 0. A pop while empty is 1 is an underflow attempt. What causes the error at C3?

Waveform for Read Attempt on an Empty FIFO. Signals: push, pop, empty, occupancy. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. push and pop are asserted together.
  2. B. occupancy becomes negative.
  3. C. pop is asserted while empty is high.
  4. D. empty remains high for more than one cycle.
Continue practicing
Waveform DebuggingFIFO Count Changes on Simultaneous Push and PopWaveform DebuggingFIFO Returns the Wrong Head EntryWaveform DebuggingFIFO Full Flag Asserts Late