Subroutines, assignments, and scheduler intent

SystemVerilog Procedural Blocks

Three layered event queues connect along an ordered timeline. — Statements become events in time.

Write executable SystemVerilog whose timing, ownership, and completion semantics remain unambiguous in simulation, synthesis, and foreign-language boundaries.

A detailed guide to tasks, functions, argument passing, lifetime, program and clocking blocks, DPI, blocking and nonblocking assignments, delays, always variants, and case intent.

18 direct practice links3 chaptersReviewed July 2026

The language bench / scheduling

Watch the update queue.

Before the edgePAUSED / 0

Pending NBA writesempty

One process starts with a=1, b=0.

Assignment operator

// One process, before the edge: a=1, b=0
a <= b;
b <= a;
#0 $display(a, b);
$strobe(a, b);

Question-first preparation

Choose a question to investigate.

Practice a real question, then inspect the mechanism in its section.

Recommended start

One representative prompt from each major mechanism. Open any card in the live question bank.

Complete question directoryFilter every stable practice link by mechanism.18 questions

Showing 18 questions across every track.Choose a track to narrow the practice set without changing its stable question links.

Inspect the concept map

Event-queue debuggerSeparate evaluation, update, and process resume.

t0RHSLHS

t+5

NonblockingActive: evaluate · NBA: update

The RHS is captured now and the LHS commits later in the same time slot.

Find a section

Chapter 1 · Subroutines & lifetime

Pick a function for a value and a task for an activity.

The distinction is not stylistic: a function must complete without consuming simulation time, while a task can synchronize, delay, and return several results through arguments.

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Chapter 1 · Subroutines & lifetime

Direction says who writes; lifetime says whether calls can overlap.

input, output, inout, ref, const ref, automatic, and static control copying, aliasing, initialization, and reentrancy. Those are observable API properties.

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Chapter 2 · Interfaces, scheduling & DPI

Race freedom comes from explicit sampling and driving contracts.

Program blocks and clocking blocks were designed to separate testbench activity from RTL updates. Modern environments still need to understand the event regions even when they use interfaces, classes, and UVM instead.

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Chapter 2 · Interfaces, scheduling & DPI

Treat the language boundary as an ABI, ownership, and state-domain contract.

DPI makes C calls convenient, not free. Direction, type mapping, open-array representation, scope, reentrancy, and context all affect correctness and performance.

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Chapter 3 · Assignments & intent

Track RHS evaluation separately from LHS update.

Blocking and nonblocking assignments, statement delays, intra-assignment delays, continuous assignments, and procedural assignments each place evaluation and update at different times.

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Chapter 3 · Assignments & intent

Let always and case variants state promises that tools can check.

always_comb, always_ff, always_latch, unique, unique0, priority, case, casez, and inside are contracts about ownership, completeness, and legal overlap—not decoration.

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Practice Procedural Blocks in the question bank →

The reasoning path

One statement · four temporal questions

Follow execution from entry through update and process resume.

A procedural statement is not fully explained until its inputs, side effects, event region, update time, and caller-visible completion are all explicit.

01Enter
Establish argument direction, lifetime, and ownership.
02Evaluate
Record when the RHS or expression is sampled.
03Update
Place the LHS effect in its real region and time slot.
04Resume
State when the caller or process may continue.

Standards and primary references

Check the contract at its source.

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