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Valid Drops During a Stall

EasyWaveform DebuggingSystemVerilog

Each column is a rising clock edge. The source drives valid and data; the receiver drives ready. Rule to apply: If valid is 1 and ready is 0 at an edge, valid must remain 1 and data must remain unchanged at the next edge. A transfer occurs only when valid and ready are both 1. What is the root cause of the protocol failure?

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Waveform for Valid Drops During a Stall. Signals: valid, ready, data. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. The receiver raises ready before valid.
  2. B. The source drops valid before the stalled beat is accepted.
  3. C. The source changes data while a transfer occurs.
  4. D. The receiver accepts two copies of the beat.
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