Skip to question

Q002FreeDesign Verification

Valid Drops During a Stall

Difficulty
Easy
Topic
Waveform Debugging
Language
SV
Interview prompt

Question

Each column shows a rising clock edge. The source drives valid and data; the receiver drives ready. If valid is 1 and ready is 0 at an edge, valid must stay 1 and data must remain unchanged at the next edge. A transfer occurs only when both valid and ready are 1. What causes the protocol failure?

Waveform for Valid Drops During a Stall. Signals: valid, ready, data. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. The receiver raises ready before valid.
  2. B. The source drops valid before the stalled beat is accepted.
  3. C. The source changes data while a transfer occurs.
  4. D. The receiver accepts two copies of the beat.
Continue practicing
Q167 · Waveform DebuggingAPB Select Drops During a Wait StateMediumQ093 · Waveform DebuggingA Single Send Command Produces Two TransfersEasyQ081 · Waveform DebuggingRead Burst Marks the Third Beat as LastMediumQ1151 · Temporal ChecksCheck payload stability during ready/valid stallsMediumP