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Hardware interview practice

Acknowledge Without an Outstanding Request

EasyWaveform DebuggingSystemVerilog

Only one request may be outstanding. A request becomes outstanding when req is sampled high and is cleared when ack is sampled high. The outstanding row shows the state immediately after each edge. Rule to apply: ack may be 1 only if a request is already outstanding or req is 1 at the same edge. Which assertion fails at C5?

Waveform for Acknowledge Without an Outstanding Request. Signals: req, ack, outstanding. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. Every req pulse must last two cycles.
  2. B. ack may be high only for an outstanding or same-cycle request.
  3. C. outstanding must stay high for the rest of simulation.
  4. D. req and ack must always rise together.